Reduced switch count multilevel inverter topology for power grid integration
This paper presents a novel and efficient topology for multilevel inverters (MLIs), specifically for power system applications, with an emphasis on minimizing the power switches count. The proposed topology integrates a cascaded configuration of three-phase traditional H-bridge inverters with a mult...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2025-09-01
|
| Series: | Results in Engineering |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2590123025017554 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1849693967948447744 |
|---|---|
| author | S. Amamra K. Meghriche A. Cherifi |
| author_facet | S. Amamra K. Meghriche A. Cherifi |
| author_sort | S. Amamra |
| collection | DOAJ |
| description | This paper presents a novel and efficient topology for multilevel inverters (MLIs), specifically for power system applications, with an emphasis on minimizing the power switches count. The proposed topology integrates a cascaded configuration of three-phase traditional H-bridge inverters with a multistring multilevel inverter. This innovative design significantly reduces harmonic distortion, energy losses, system dimensions, and both the cost and complexity of the hardware, key considerations for practical grid integration. Simulations conducted in MATLAB/Simulink verify the proposed topology’s capability to achieve up to six, twelve and eighteen voltage levels with the connection of only three, five and seven DC sources. This feature offers substantial improvements in power quality and overall system efficiency. Experimental validation of the developed prototype further confirms a notable reduction in harmonic distortion, achieving an approximate 15 % and 1.2 % voltage and current THD respectively. These findings highlight the effectiveness of the proposed topology in enhancing grid integration performance by minimizing undesirable harmonics and improving system reliability and sustainability. Additionally, the simplified hardware and cost-efficiency position this approach as a promising solution for large-scale different DC sources integration into power grid. |
| format | Article |
| id | doaj-art-e09ded10f80343afbf9bc5fcad197c55 |
| institution | DOAJ |
| issn | 2590-1230 |
| language | English |
| publishDate | 2025-09-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Results in Engineering |
| spelling | doaj-art-e09ded10f80343afbf9bc5fcad197c552025-08-20T03:20:15ZengElsevierResults in Engineering2590-12302025-09-012710568410.1016/j.rineng.2025.105684Reduced switch count multilevel inverter topology for power grid integrationS. Amamra0K. Meghriche1A. Cherifi2School of Computing and Engineering, University of Huddersfield, Huddersfield, UK; Corresponding author.Université Paris-Saclay, UVSQ, LISV, 78140, Vélizy-Villacoublay, FranceUniversité Paris-Saclay, UVSQ, Inserm, END-ICAP, 78000, Versailles, FranceThis paper presents a novel and efficient topology for multilevel inverters (MLIs), specifically for power system applications, with an emphasis on minimizing the power switches count. The proposed topology integrates a cascaded configuration of three-phase traditional H-bridge inverters with a multistring multilevel inverter. This innovative design significantly reduces harmonic distortion, energy losses, system dimensions, and both the cost and complexity of the hardware, key considerations for practical grid integration. Simulations conducted in MATLAB/Simulink verify the proposed topology’s capability to achieve up to six, twelve and eighteen voltage levels with the connection of only three, five and seven DC sources. This feature offers substantial improvements in power quality and overall system efficiency. Experimental validation of the developed prototype further confirms a notable reduction in harmonic distortion, achieving an approximate 15 % and 1.2 % voltage and current THD respectively. These findings highlight the effectiveness of the proposed topology in enhancing grid integration performance by minimizing undesirable harmonics and improving system reliability and sustainability. Additionally, the simplified hardware and cost-efficiency position this approach as a promising solution for large-scale different DC sources integration into power grid.http://www.sciencedirect.com/science/article/pii/S2590123025017554InvertersMultilevel topologySwitchesSwitching lossSwitching frequency |
| spellingShingle | S. Amamra K. Meghriche A. Cherifi Reduced switch count multilevel inverter topology for power grid integration Results in Engineering Inverters Multilevel topology Switches Switching loss Switching frequency |
| title | Reduced switch count multilevel inverter topology for power grid integration |
| title_full | Reduced switch count multilevel inverter topology for power grid integration |
| title_fullStr | Reduced switch count multilevel inverter topology for power grid integration |
| title_full_unstemmed | Reduced switch count multilevel inverter topology for power grid integration |
| title_short | Reduced switch count multilevel inverter topology for power grid integration |
| title_sort | reduced switch count multilevel inverter topology for power grid integration |
| topic | Inverters Multilevel topology Switches Switching loss Switching frequency |
| url | http://www.sciencedirect.com/science/article/pii/S2590123025017554 |
| work_keys_str_mv | AT samamra reducedswitchcountmultilevelinvertertopologyforpowergridintegration AT kmeghriche reducedswitchcountmultilevelinvertertopologyforpowergridintegration AT acherifi reducedswitchcountmultilevelinvertertopologyforpowergridintegration |