An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications
Abstract In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumpti...
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Wiley
2022-07-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/cds2.12112 |
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| author | Hamid Mahmoodian Mehdi Dolatshahi S. Mohammadali Zanjani Mohammad Amin Honarvar |
| author_facet | Hamid Mahmoodian Mehdi Dolatshahi S. Mohammadali Zanjani Mohammad Amin Honarvar |
| author_sort | Hamid Mahmoodian |
| collection | DOAJ |
| description | Abstract In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumption and high‐speed performances. The proposed speed‐up technique for the latch structure controls the threshold voltage (Vth) of the cross‐coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double‐tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double‐tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed‐up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high‐resolution (up to 12 bit) and high‐speed low‐power analogue‐to‐digital converter applications. Moreover, the effects of the non‐ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte‐Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs. |
| format | Article |
| id | doaj-art-df9f4b8b076744a985a296bcf4551311 |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2022-07-01 |
| publisher | Wiley |
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| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-df9f4b8b076744a985a296bcf45513112025-02-03T01:29:37ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982022-07-0116436037110.1049/cds2.12112An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applicationsHamid Mahmoodian0Mehdi Dolatshahi1S. Mohammadali Zanjani2Mohammad Amin Honarvar3Department of Electrical Engineering Najafabad Branch, Islamic Azad University Najafabad IranDepartment of Electrical Engineering Najafabad Branch, Islamic Azad University Najafabad IranDepartment of Electrical Engineering Najafabad Branch, Islamic Azad University Najafabad IranDepartment of Electrical Engineering Najafabad Branch, Islamic Azad University Najafabad IranAbstract In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumption and high‐speed performances. The proposed speed‐up technique for the latch structure controls the threshold voltage (Vth) of the cross‐coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double‐tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double‐tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed‐up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high‐resolution (up to 12 bit) and high‐speed low‐power analogue‐to‐digital converter applications. Moreover, the effects of the non‐ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte‐Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.https://doi.org/10.1049/cds2.12112analogue‐to‐digital converter (ADC)CNTFETdynamic comparatorhigh‐speedlow‐power |
| spellingShingle | Hamid Mahmoodian Mehdi Dolatshahi S. Mohammadali Zanjani Mohammad Amin Honarvar An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications IET Circuits, Devices and Systems analogue‐to‐digital converter (ADC) CNTFET dynamic comparator high‐speed low‐power |
| title | An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications |
| title_full | An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications |
| title_fullStr | An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications |
| title_full_unstemmed | An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications |
| title_short | An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications |
| title_sort | energy efficient dynamic comparator in carbon nanotube field effect transistor technology for successive approximation register adc applications |
| topic | analogue‐to‐digital converter (ADC) CNTFET dynamic comparator high‐speed low‐power |
| url | https://doi.org/10.1049/cds2.12112 |
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