Exact Analysis and Physical Realization of the 6-Lobe Chua Corsage Memristor
A novel generic memristor, dubbed the 6-lobe Chua corsage memristor, is proposed with its nonlinear dynamical analysis and physical realization. The proposed corsage memristor contains four asymptotically stable equilibrium points on its complex and diversified dynamic routes which reveals a 4-state...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2018-01-01
|
| Series: | Complexity |
| Online Access: | http://dx.doi.org/10.1155/2018/8405978 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1849435143845969920 |
|---|---|
| author | Zubaer I. Mannan Changju Yang Shyam P. Adhikari Hyongsuk Kim |
| author_facet | Zubaer I. Mannan Changju Yang Shyam P. Adhikari Hyongsuk Kim |
| author_sort | Zubaer I. Mannan |
| collection | DOAJ |
| description | A novel generic memristor, dubbed the 6-lobe Chua corsage memristor, is proposed with its nonlinear dynamical analysis and physical realization. The proposed corsage memristor contains four asymptotically stable equilibrium points on its complex and diversified dynamic routes which reveals a 4-state nonlinear memory device. The higher degree of versatility of its dynamic routes reveal that the proposed memristor has a variety of dynamic paths in response to different initial conditions and exhibits a highly nonlinear contiguous DC V-I curve. The DC V-I curve of the proposed memristor is endowed with an explicit analytical parametric representation. Moreover, the derived three formulas, exponential trajectories of state xnt, time period tfn, and minimum pulse amplitude VA, are required to analyze the movement of the state trajectories on the piecewise linear (PWL) dynamic route map (DRM) of the corsage memristor. These formulas are universal, that is, applicable to any PWL DRM curves for any DC or pulse input and with any number of segments. Nonlinear dynamics and circuit and system theoretic approach are employed to explain the asymptotic quad-stable behavior of the proposed corsage memristor and to design a novel real memristor emulator using off-the-shelf circuit components. |
| format | Article |
| id | doaj-art-df535c53c0ca40e3b1e09a652f38e9ba |
| institution | Kabale University |
| issn | 1076-2787 1099-0526 |
| language | English |
| publishDate | 2018-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Complexity |
| spelling | doaj-art-df535c53c0ca40e3b1e09a652f38e9ba2025-08-20T03:26:25ZengWileyComplexity1076-27871099-05262018-01-01201810.1155/2018/84059788405978Exact Analysis and Physical Realization of the 6-Lobe Chua Corsage MemristorZubaer I. Mannan0Changju Yang1Shyam P. Adhikari2Hyongsuk Kim3Division of Electronics and Information Engineering and Intelligent Robots Research Center (IRRC), Chonbuk National University, Jeonju, Jeonbuk 567-54896, Republic of KoreaDivision of Electronics and Information Engineering and Intelligent Robots Research Center (IRRC), Chonbuk National University, Jeonju, Jeonbuk 567-54896, Republic of KoreaDivision of Electronics and Information Engineering and Intelligent Robots Research Center (IRRC), Chonbuk National University, Jeonju, Jeonbuk 567-54896, Republic of KoreaDivision of Electronics and Information Engineering and Intelligent Robots Research Center (IRRC), Chonbuk National University, Jeonju, Jeonbuk 567-54896, Republic of KoreaA novel generic memristor, dubbed the 6-lobe Chua corsage memristor, is proposed with its nonlinear dynamical analysis and physical realization. The proposed corsage memristor contains four asymptotically stable equilibrium points on its complex and diversified dynamic routes which reveals a 4-state nonlinear memory device. The higher degree of versatility of its dynamic routes reveal that the proposed memristor has a variety of dynamic paths in response to different initial conditions and exhibits a highly nonlinear contiguous DC V-I curve. The DC V-I curve of the proposed memristor is endowed with an explicit analytical parametric representation. Moreover, the derived three formulas, exponential trajectories of state xnt, time period tfn, and minimum pulse amplitude VA, are required to analyze the movement of the state trajectories on the piecewise linear (PWL) dynamic route map (DRM) of the corsage memristor. These formulas are universal, that is, applicable to any PWL DRM curves for any DC or pulse input and with any number of segments. Nonlinear dynamics and circuit and system theoretic approach are employed to explain the asymptotic quad-stable behavior of the proposed corsage memristor and to design a novel real memristor emulator using off-the-shelf circuit components.http://dx.doi.org/10.1155/2018/8405978 |
| spellingShingle | Zubaer I. Mannan Changju Yang Shyam P. Adhikari Hyongsuk Kim Exact Analysis and Physical Realization of the 6-Lobe Chua Corsage Memristor Complexity |
| title | Exact Analysis and Physical Realization of the 6-Lobe Chua Corsage Memristor |
| title_full | Exact Analysis and Physical Realization of the 6-Lobe Chua Corsage Memristor |
| title_fullStr | Exact Analysis and Physical Realization of the 6-Lobe Chua Corsage Memristor |
| title_full_unstemmed | Exact Analysis and Physical Realization of the 6-Lobe Chua Corsage Memristor |
| title_short | Exact Analysis and Physical Realization of the 6-Lobe Chua Corsage Memristor |
| title_sort | exact analysis and physical realization of the 6 lobe chua corsage memristor |
| url | http://dx.doi.org/10.1155/2018/8405978 |
| work_keys_str_mv | AT zubaerimannan exactanalysisandphysicalrealizationofthe6lobechuacorsagememristor AT changjuyang exactanalysisandphysicalrealizationofthe6lobechuacorsagememristor AT shyampadhikari exactanalysisandphysicalrealizationofthe6lobechuacorsagememristor AT hyongsukkim exactanalysisandphysicalrealizationofthe6lobechuacorsagememristor |