Optimization and Characterization of CMOS for Ultra Low Power Applications
Aggressive voltage scaling into the subthreshold operating region holds great promise for applications with strict energy budget. However, it has been established that higher speed superthreshold device is not suitable for moderate performance subthreshold circuits. The design constraint for selecti...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2015-01-01
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| Series: | Journal of Nanotechnology |
| Online Access: | http://dx.doi.org/10.1155/2015/395090 |
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| _version_ | 1849468003411820544 |
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| author | Mohd. Ajmal Kafeel S. D. Pable Mohd. Hasan M. Shah Alam |
| author_facet | Mohd. Ajmal Kafeel S. D. Pable Mohd. Hasan M. Shah Alam |
| author_sort | Mohd. Ajmal Kafeel |
| collection | DOAJ |
| description | Aggressive voltage scaling into the subthreshold operating region holds great promise for applications with strict energy budget. However, it has been established that higher speed superthreshold device is not suitable for moderate performance subthreshold circuits. The design constraint for selecting Vth and TOX is much more flexible for subthreshold circuits at low voltage level than superthreshold circuits. In order to obtain better performance from a device under subthreshold conditions, it is necessary to investigate and optimize the process and geometry parameters of a Si MOSFET at nanometer technology node. This paper calibrates the fabrication process parameters and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length. Thereafter, the calibrated device for superthreshold application is optimized for better performance under subthreshold conditions using TCAD simulation. The device simulated in this work shows 9.89% improvement in subthreshold slope and 34% advantage in ION/IOFF ratio for the same drive current. |
| format | Article |
| id | doaj-art-df50d2764a0d481a9315ee617b30a71c |
| institution | Kabale University |
| issn | 1687-9503 1687-9511 |
| language | English |
| publishDate | 2015-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Nanotechnology |
| spelling | doaj-art-df50d2764a0d481a9315ee617b30a71c2025-08-20T03:25:59ZengWileyJournal of Nanotechnology1687-95031687-95112015-01-01201510.1155/2015/395090395090Optimization and Characterization of CMOS for Ultra Low Power ApplicationsMohd. Ajmal Kafeel0S. D. Pable1Mohd. Hasan2M. Shah Alam3Department of Electronics Engineering, AMU, Aligarh, IndiaDepartment of Electronics and Telecommunication Engineering, Matoshri College of Engineering and Research Centre, Eklahare, Nashik, Maharashtra, IndiaDepartment of Electronics Engineering, AMU, Aligarh, IndiaDepartment of Electronics Engineering, AMU, Aligarh, IndiaAggressive voltage scaling into the subthreshold operating region holds great promise for applications with strict energy budget. However, it has been established that higher speed superthreshold device is not suitable for moderate performance subthreshold circuits. The design constraint for selecting Vth and TOX is much more flexible for subthreshold circuits at low voltage level than superthreshold circuits. In order to obtain better performance from a device under subthreshold conditions, it is necessary to investigate and optimize the process and geometry parameters of a Si MOSFET at nanometer technology node. This paper calibrates the fabrication process parameters and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length. Thereafter, the calibrated device for superthreshold application is optimized for better performance under subthreshold conditions using TCAD simulation. The device simulated in this work shows 9.89% improvement in subthreshold slope and 34% advantage in ION/IOFF ratio for the same drive current.http://dx.doi.org/10.1155/2015/395090 |
| spellingShingle | Mohd. Ajmal Kafeel S. D. Pable Mohd. Hasan M. Shah Alam Optimization and Characterization of CMOS for Ultra Low Power Applications Journal of Nanotechnology |
| title | Optimization and Characterization of CMOS for Ultra Low Power Applications |
| title_full | Optimization and Characterization of CMOS for Ultra Low Power Applications |
| title_fullStr | Optimization and Characterization of CMOS for Ultra Low Power Applications |
| title_full_unstemmed | Optimization and Characterization of CMOS for Ultra Low Power Applications |
| title_short | Optimization and Characterization of CMOS for Ultra Low Power Applications |
| title_sort | optimization and characterization of cmos for ultra low power applications |
| url | http://dx.doi.org/10.1155/2015/395090 |
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