Interface design of HART modulation and demodulation chip
In order to adapt to the current factory equipment, aiming at the huge amount of equipment and data transmission, this paper designs a new HART modulation and demodulation core interface, which uses AXI4 bus interface to replace the traditional UART interface to accelerate the communication speed be...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | zho |
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National Computer System Engineering Research Institute of China
2022-04-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000148309 |
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| _version_ | 1850082690360934400 |
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| author | Zhang Liguo Li Fukun Yan Wei Liu Qiang Wang Xuedi |
| author_facet | Zhang Liguo Li Fukun Yan Wei Liu Qiang Wang Xuedi |
| author_sort | Zhang Liguo |
| collection | DOAJ |
| description | In order to adapt to the current factory equipment, aiming at the huge amount of equipment and data transmission, this paper designs a new HART modulation and demodulation core interface, which uses AXI4 bus interface to replace the traditional UART interface to accelerate the communication speed between HART modulation and demodulation chip and CPU. Compared to the traditional URAT interface, the AXI4 bus interface can transmit 32 bits of 8 bytes in parallel, and the data transfer speed can reach the NS level. Through the interconnection of AXI4 bus module and CPU, the structure function configuration and data interaction are realized. The high-speed communication interface design of HART modulation and demodulation chip was verified based on FPGA platform. The results show that the architecture can effectively identify HART communication protocol, the data interaction between CPU and HART chip reaches NS level, and the correct rate of modulation and demodulation reaches 100%, which meets the requirements of HART communication protocol. |
| format | Article |
| id | doaj-art-ddd013b97d3c4a6f9ba702b40ce3e202 |
| institution | DOAJ |
| issn | 0258-7998 |
| language | zho |
| publishDate | 2022-04-01 |
| publisher | National Computer System Engineering Research Institute of China |
| record_format | Article |
| series | Dianzi Jishu Yingyong |
| spelling | doaj-art-ddd013b97d3c4a6f9ba702b40ce3e2022025-08-20T02:44:28ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982022-04-0148461110.16157/j.issn.0258-7998.2115513000148309Interface design of HART modulation and demodulation chipZhang Liguo0Li Fukun1Yan Wei2Liu Qiang3Wang Xuedi4School of Electrical Engineering，Yanshan University，Qinhuangdao 066000，ChinaSchool of Electrical Engineering，Yanshan University，Qinhuangdao 066000，ChinaSchool of Software and Microelectronics，Peking University，Beijing 100871，ChinaSchool of Electrical Engineering，Yanshan University，Qinhuangdao 066000，ChinaSchool of Software and Microelectronics，Peking University，Beijing 100871，ChinaIn order to adapt to the current factory equipment, aiming at the huge amount of equipment and data transmission, this paper designs a new HART modulation and demodulation core interface, which uses AXI4 bus interface to replace the traditional UART interface to accelerate the communication speed between HART modulation and demodulation chip and CPU. Compared to the traditional URAT interface, the AXI4 bus interface can transmit 32 bits of 8 bytes in parallel, and the data transfer speed can reach the NS level. Through the interconnection of AXI4 bus module and CPU, the structure function configuration and data interaction are realized. The high-speed communication interface design of HART modulation and demodulation chip was verified based on FPGA platform. The results show that the architecture can effectively identify HART communication protocol, the data interaction between CPU and HART chip reaches NS level, and the correct rate of modulation and demodulation reaches 100%, which meets the requirements of HART communication protocol.http://www.chinaaet.com/article/3000148309communication chip architecturechip interconnectionhart communication protocolcommunication interface |
| spellingShingle | Zhang Liguo Li Fukun Yan Wei Liu Qiang Wang Xuedi Interface design of HART modulation and demodulation chip Dianzi Jishu Yingyong communication chip architecture chip interconnection hart communication protocol communication interface |
| title | Interface design of HART modulation and demodulation chip |
| title_full | Interface design of HART modulation and demodulation chip |
| title_fullStr | Interface design of HART modulation and demodulation chip |
| title_full_unstemmed | Interface design of HART modulation and demodulation chip |
| title_short | Interface design of HART modulation and demodulation chip |
| title_sort | interface design of hart modulation and demodulation chip |
| topic | communication chip architecture chip interconnection hart communication protocol communication interface |
| url | http://www.chinaaet.com/article/3000148309 |
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