Interfacial Chemical and Electrical Performance Study and Thermal Annealing Refinement for AlTiO/4H-SiC MOS Capacitors
The gate reliability issues in SiC-based devices with a gate dielectric formed through heat oxidation are important factors limiting their application in power devices. Aluminum oxide (Al<sub>2</sub>O<sub>3</sub>) and titanium dioxide (TiO<sub>2</sub>) were combin...
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2025-05-01
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| author | Yu-Xuan Zeng Wei Huang Hong-Ping Ma Qing-Chun Zhang |
| author_facet | Yu-Xuan Zeng Wei Huang Hong-Ping Ma Qing-Chun Zhang |
| author_sort | Yu-Xuan Zeng |
| collection | DOAJ |
| description | The gate reliability issues in SiC-based devices with a gate dielectric formed through heat oxidation are important factors limiting their application in power devices. Aluminum oxide (Al<sub>2</sub>O<sub>3</sub>) and titanium dioxide (TiO<sub>2</sub>) were combined using the ALD process to form a composite AlTiO gate dielectric on a 4H-SiC substrate. TDMAT and TMA were the precursors selected and deposited at 200 °C, and the samples were Ar or N<sub>2</sub> annealed at temperatures ranging from 300 °C to 700 °C. An XPS analysis suggested that the AlTiO film had been deposited with a high overall quality and the involvement of Ti atoms had increased the interfacial bonding with the substrate. The as-deposited MOS structure had band shifts of Δ<i>E</i><sub>C</sub> = 1.08 eV and Δ<i>E</i><sub>V</sub> = 2.41 eV. After annealing, the AlTiO bandgap increased by 0.85 eV at most, and better band alignment was attained. Leakage current and breakdown voltage characteristic investigations were conducted after Al electrode deposition. The leakage current density and electrical breakdown field of an MOS capacitor structure with a SiC substrate were ~10<sup>−3</sup> A/cm<sup>2</sup> and 6.3 MV/cm, respectively. After the annealing process, both the measures of the JV performance of the MOS capacitor had improved to ~10<sup>−6</sup> A/cm<sup>2</sup> and 7.2 MV/cm. The interface charge <i>N</i><sub>eff</sub> of the AlTiO layer was 4.019 × 10<sup>10</sup> cm<sup>−2</sup>. The AlTiO/SiC structure fabricated in this work proved the feasibility of adjusting the properties of single-component gate dielectric materials using the ALD method, and using a suitable thermal annealing process has great potential to improve the performance of the compound MOS dielectric layer. |
| format | Article |
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| institution | DOAJ |
| issn | 2079-4991 |
| language | English |
| publishDate | 2025-05-01 |
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| series | Nanomaterials |
| spelling | doaj-art-dcd5d9dd92b44b75a5ef1949bd3557c02025-08-20T03:11:22ZengMDPI AGNanomaterials2079-49912025-05-01151181410.3390/nano15110814Interfacial Chemical and Electrical Performance Study and Thermal Annealing Refinement for AlTiO/4H-SiC MOS CapacitorsYu-Xuan Zeng0Wei Huang1Hong-Ping Ma2Qing-Chun Zhang3Institute of Wide Bandgap Semiconductors and Future Lighting, Academy for Engineering & Technology, Fudan University, Shanghai 200433, ChinaInstitute of Wide Bandgap Semiconductors and Future Lighting, Academy for Engineering & Technology, Fudan University, Shanghai 200433, ChinaInstitute of Wide Bandgap Semiconductors and Future Lighting, Academy for Engineering & Technology, Fudan University, Shanghai 200433, ChinaInstitute of Wide Bandgap Semiconductors and Future Lighting, Academy for Engineering & Technology, Fudan University, Shanghai 200433, ChinaThe gate reliability issues in SiC-based devices with a gate dielectric formed through heat oxidation are important factors limiting their application in power devices. Aluminum oxide (Al<sub>2</sub>O<sub>3</sub>) and titanium dioxide (TiO<sub>2</sub>) were combined using the ALD process to form a composite AlTiO gate dielectric on a 4H-SiC substrate. TDMAT and TMA were the precursors selected and deposited at 200 °C, and the samples were Ar or N<sub>2</sub> annealed at temperatures ranging from 300 °C to 700 °C. An XPS analysis suggested that the AlTiO film had been deposited with a high overall quality and the involvement of Ti atoms had increased the interfacial bonding with the substrate. The as-deposited MOS structure had band shifts of Δ<i>E</i><sub>C</sub> = 1.08 eV and Δ<i>E</i><sub>V</sub> = 2.41 eV. After annealing, the AlTiO bandgap increased by 0.85 eV at most, and better band alignment was attained. Leakage current and breakdown voltage characteristic investigations were conducted after Al electrode deposition. The leakage current density and electrical breakdown field of an MOS capacitor structure with a SiC substrate were ~10<sup>−3</sup> A/cm<sup>2</sup> and 6.3 MV/cm, respectively. After the annealing process, both the measures of the JV performance of the MOS capacitor had improved to ~10<sup>−6</sup> A/cm<sup>2</sup> and 7.2 MV/cm. The interface charge <i>N</i><sub>eff</sub> of the AlTiO layer was 4.019 × 10<sup>10</sup> cm<sup>−2</sup>. The AlTiO/SiC structure fabricated in this work proved the feasibility of adjusting the properties of single-component gate dielectric materials using the ALD method, and using a suitable thermal annealing process has great potential to improve the performance of the compound MOS dielectric layer.https://www.mdpi.com/2079-4991/15/11/814high-k materialAlTiO4H-SiCgate dielectricinterface state |
| spellingShingle | Yu-Xuan Zeng Wei Huang Hong-Ping Ma Qing-Chun Zhang Interfacial Chemical and Electrical Performance Study and Thermal Annealing Refinement for AlTiO/4H-SiC MOS Capacitors Nanomaterials high-k material AlTiO 4H-SiC gate dielectric interface state |
| title | Interfacial Chemical and Electrical Performance Study and Thermal Annealing Refinement for AlTiO/4H-SiC MOS Capacitors |
| title_full | Interfacial Chemical and Electrical Performance Study and Thermal Annealing Refinement for AlTiO/4H-SiC MOS Capacitors |
| title_fullStr | Interfacial Chemical and Electrical Performance Study and Thermal Annealing Refinement for AlTiO/4H-SiC MOS Capacitors |
| title_full_unstemmed | Interfacial Chemical and Electrical Performance Study and Thermal Annealing Refinement for AlTiO/4H-SiC MOS Capacitors |
| title_short | Interfacial Chemical and Electrical Performance Study and Thermal Annealing Refinement for AlTiO/4H-SiC MOS Capacitors |
| title_sort | interfacial chemical and electrical performance study and thermal annealing refinement for altio 4h sic mos capacitors |
| topic | high-k material AlTiO 4H-SiC gate dielectric interface state |
| url | https://www.mdpi.com/2079-4991/15/11/814 |
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