Integration in CNN and FIR filters for improved computational efficiency in signal processing
This research paper explains the design process of the 8 × 8 Vedic multipliers based on the “UrdhvaTiryagbhyam” Sutra in combination with the “Nikhilam Sutra“ and the Karatsuba algorithm. To effectively generate a 16-bit product, the used architecture consists of four four-by-four Vedic modules, an...
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Elsevier
2025-01-01
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| Series: | Ain Shams Engineering Journal |
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| Online Access: | http://www.sciencedirect.com/science/article/pii/S2090447924005823 |
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| author | A. Sridevi A. Sathiya |
| author_facet | A. Sridevi A. Sathiya |
| author_sort | A. Sridevi |
| collection | DOAJ |
| description | This research paper explains the design process of the 8 × 8 Vedic multipliers based on the “UrdhvaTiryagbhyam” Sutra in combination with the “Nikhilam Sutra“ and the Karatsuba algorithm. To effectively generate a 16-bit product, the used architecture consists of four four-by-four Vedic modules, an 8:1 carry-save adder, and two nine-bit binary adders. The UrdhvaTiryagbhyam approach splits multiplications into pieces, the Nikhilam Sutra uses the concept of binary complements, and the Karatsuba algorithm offers improvements in large numbers of multiplications. The proposed addition microarchitecture, which consists of using a Fast Carry Switching Adder and the Kogge-Stone Adder with associated selection signals and speculative logic, improves carry propagation time. The ability of the Vedic multiplier is tested within an FIR filter and a CNN processing element, revealing significant enhancements in speed and efficiency. Importantly, the proposed multiplier based on the modification of Vedic Nikhilam yields the lowest power consumption (248.93 mW), the lowest delay (27.95 ns), and the lowest PDP (6.96 pJ), thus making it appropriate for usage in HPC related to signal processing and neural network computations. Moreover, the developed FIR filter for the CNN and the EEG signal datasets were employed to detect seizures and Alzheimer’s disease. The incorporation of the Vedic multiplier into the CNN framework reveals the application of the proposed idea in the field of biomedical signal processing with improved computational speed and accuracy. The results corroborate the multiplier’s efficiency in decreasing the computational complexity and enhancing the possibility of real-time analysis of CNN-based systems in healthcare. |
| format | Article |
| id | doaj-art-dc934851cbeb4da9bc1664f02900162f |
| institution | Kabale University |
| issn | 2090-4479 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Ain Shams Engineering Journal |
| spelling | doaj-art-dc934851cbeb4da9bc1664f02900162f2025-01-17T04:49:23ZengElsevierAin Shams Engineering Journal2090-44792025-01-01161103201Integration in CNN and FIR filters for improved computational efficiency in signal processingA. Sridevi0A. Sathiya1Corresponding author.; Department of Electronics and Communication Engineering, M.Kumarasamy College of Engineering (Autonomous), Karur, Tamil Nadu 639113, IndiaDepartment of Electronics and Communication Engineering, M.Kumarasamy College of Engineering (Autonomous), Karur, Tamil Nadu 639113, IndiaThis research paper explains the design process of the 8 × 8 Vedic multipliers based on the “UrdhvaTiryagbhyam” Sutra in combination with the “Nikhilam Sutra“ and the Karatsuba algorithm. To effectively generate a 16-bit product, the used architecture consists of four four-by-four Vedic modules, an 8:1 carry-save adder, and two nine-bit binary adders. The UrdhvaTiryagbhyam approach splits multiplications into pieces, the Nikhilam Sutra uses the concept of binary complements, and the Karatsuba algorithm offers improvements in large numbers of multiplications. The proposed addition microarchitecture, which consists of using a Fast Carry Switching Adder and the Kogge-Stone Adder with associated selection signals and speculative logic, improves carry propagation time. The ability of the Vedic multiplier is tested within an FIR filter and a CNN processing element, revealing significant enhancements in speed and efficiency. Importantly, the proposed multiplier based on the modification of Vedic Nikhilam yields the lowest power consumption (248.93 mW), the lowest delay (27.95 ns), and the lowest PDP (6.96 pJ), thus making it appropriate for usage in HPC related to signal processing and neural network computations. Moreover, the developed FIR filter for the CNN and the EEG signal datasets were employed to detect seizures and Alzheimer’s disease. The incorporation of the Vedic multiplier into the CNN framework reveals the application of the proposed idea in the field of biomedical signal processing with improved computational speed and accuracy. The results corroborate the multiplier’s efficiency in decreasing the computational complexity and enhancing the possibility of real-time analysis of CNN-based systems in healthcare.http://www.sciencedirect.com/science/article/pii/S2090447924005823FIR filterCNNNikhilam SutraKaratsuba algorithmFilter coefficientFast Carry Switching Adder |
| spellingShingle | A. Sridevi A. Sathiya Integration in CNN and FIR filters for improved computational efficiency in signal processing Ain Shams Engineering Journal FIR filter CNN Nikhilam Sutra Karatsuba algorithm Filter coefficient Fast Carry Switching Adder |
| title | Integration in CNN and FIR filters for improved computational efficiency in signal processing |
| title_full | Integration in CNN and FIR filters for improved computational efficiency in signal processing |
| title_fullStr | Integration in CNN and FIR filters for improved computational efficiency in signal processing |
| title_full_unstemmed | Integration in CNN and FIR filters for improved computational efficiency in signal processing |
| title_short | Integration in CNN and FIR filters for improved computational efficiency in signal processing |
| title_sort | integration in cnn and fir filters for improved computational efficiency in signal processing |
| topic | FIR filter CNN Nikhilam Sutra Karatsuba algorithm Filter coefficient Fast Carry Switching Adder |
| url | http://www.sciencedirect.com/science/article/pii/S2090447924005823 |
| work_keys_str_mv | AT asridevi integrationincnnandfirfiltersforimprovedcomputationalefficiencyinsignalprocessing AT asathiya integrationincnnandfirfiltersforimprovedcomputationalefficiencyinsignalprocessing |