Analysis and Verilog-A Modeling of Floating-Gate Transistors

Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circu...

Full description

Saved in:
Bibliographic Details
Main Authors: Sayma Nowshin Chowdhury, Matthew Chen, Sahil Shah
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Open Journal of Circuits and Systems
Subjects:
Online Access:https://ieeexplore.ieee.org/document/10818976/
Tags: Add Tag
No Tags, Be the first to tag this record!
_version_ 1832590361399132160
author Sayma Nowshin Chowdhury
Matthew Chen
Sahil Shah
author_facet Sayma Nowshin Chowdhury
Matthew Chen
Sahil Shah
author_sort Sayma Nowshin Chowdhury
collection DOAJ
description Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circuits typically involves extensive SPICE-based simulations, yet integrating and calibrating floating-gate transistors post-fabrication is a common practice. To bridge this gap, we present a Verilog-A model based on empirical measurements for a floating-gate transistor fabricated using a 65 nm CMOS process. This model incorporates mechanisms for hot-electron injection and Fowler-Nordheim tunneling, and accurately predicts retention time, thus facilitating the design of adaptive peripheral circuits. Our findings offer insights into optimizing floating-gate transistors for enhanced programming efficiency and reduced area consumption.
format Article
id doaj-art-db997ee9b9b44b369fe82051872dde48
institution Kabale University
issn 2644-1225
language English
publishDate 2025-01-01
publisher IEEE
record_format Article
series IEEE Open Journal of Circuits and Systems
spelling doaj-art-db997ee9b9b44b369fe82051872dde482025-01-24T00:02:30ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252025-01-016637310.1109/OJCAS.2024.352436310818976Analysis and Verilog-A Modeling of Floating-Gate TransistorsSayma Nowshin Chowdhury0https://orcid.org/0009-0005-3103-032XMatthew Chen1https://orcid.org/0009-0003-4127-9327Sahil Shah2https://orcid.org/0000-0001-7403-2388Department of Electrical and Computer Engineering, University of Maryland, College Park, MD, USADepartment of Electrical and Computer Engineering, University of Maryland, College Park, MD, USADepartment of Electrical and Computer Engineering, University of Maryland, College Park, MD, USAFloating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circuits typically involves extensive SPICE-based simulations, yet integrating and calibrating floating-gate transistors post-fabrication is a common practice. To bridge this gap, we present a Verilog-A model based on empirical measurements for a floating-gate transistor fabricated using a 65 nm CMOS process. This model incorporates mechanisms for hot-electron injection and Fowler-Nordheim tunneling, and accurately predicts retention time, thus facilitating the design of adaptive peripheral circuits. Our findings offer insights into optimizing floating-gate transistors for enhanced programming efficiency and reduced area consumption.https://ieeexplore.ieee.org/document/10818976/Floating-gate transistorsVerilog-Aanalog synapses
spellingShingle Sayma Nowshin Chowdhury
Matthew Chen
Sahil Shah
Analysis and Verilog-A Modeling of Floating-Gate Transistors
IEEE Open Journal of Circuits and Systems
Floating-gate transistors
Verilog-A
analog synapses
title Analysis and Verilog-A Modeling of Floating-Gate Transistors
title_full Analysis and Verilog-A Modeling of Floating-Gate Transistors
title_fullStr Analysis and Verilog-A Modeling of Floating-Gate Transistors
title_full_unstemmed Analysis and Verilog-A Modeling of Floating-Gate Transistors
title_short Analysis and Verilog-A Modeling of Floating-Gate Transistors
title_sort analysis and verilog a modeling of floating gate transistors
topic Floating-gate transistors
Verilog-A
analog synapses
url https://ieeexplore.ieee.org/document/10818976/
work_keys_str_mv AT saymanowshinchowdhury analysisandverilogamodelingoffloatinggatetransistors
AT matthewchen analysisandverilogamodelingoffloatinggatetransistors
AT sahilshah analysisandverilogamodelingoffloatinggatetransistors