CMOS Single-Photon Avalanche Diode Circuits for Probabilistic Computing

Intrinsically random hardware devices are increasingly attracting attention for their potential use in probabilistic computing architectures. One such device is the single-photon avalanche diode (SPAD) and an associated functional unit, the variable-rate SPAD circuit (VRSC), recently proposed by us...

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Main Authors: William Whitehead, Wonsik Oh, Luke Theogarajan
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
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Online Access:https://ieeexplore.ieee.org/document/10659028/
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author William Whitehead
Wonsik Oh
Luke Theogarajan
author_facet William Whitehead
Wonsik Oh
Luke Theogarajan
author_sort William Whitehead
collection DOAJ
description Intrinsically random hardware devices are increasingly attracting attention for their potential use in probabilistic computing architectures. One such device is the single-photon avalanche diode (SPAD) and an associated functional unit, the variable-rate SPAD circuit (VRSC), recently proposed by us as a source of randomness for sampling and annealing Ising and Potts models. This work develops a more advanced understanding of these VRSCs by introducing several VRSC design options and studying their tradeoffs as implemented in a 65-nm CMOS process. Each VRSC is composed of a SPAD and a processing circuit. Combinations of three different SPAD designs and three different types of processing circuits were evaluated on several metrics such as area, speed, and variability. Measured results from the SPAD design space show that even extremely small SPADs are suitable for probabilistic computing purposes, and that high dark count rates are not detrimental either, so SPADs for probabilistic computing are actually easier to integrate in standard CMOS processes. Results from the circuit design space show that the time-to-analog-based designs introduced in this work can produce highly exponential and analytical transfer functions, but that the less analytically tractable output of the previously proposed filter-based designs can achieve less variability in a smaller footprint. Probabilistic bits (P-bits) composed of the fabricated VRSCs achieve bit flip rates of 50 MHz and allow at least one order of magnitude of control over their simulated annealing temperature.
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spelling doaj-art-da6d34822e134364a60ff2a34e94ae0f2025-01-21T00:02:32ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312024-01-0110495710.1109/JXCDC.2024.345203010659028CMOS Single-Photon Avalanche Diode Circuits for Probabilistic ComputingWilliam Whitehead0https://orcid.org/0009-0000-0781-5104Wonsik Oh1https://orcid.org/0009-0001-5678-7346Luke Theogarajan2https://orcid.org/0000-0002-0320-5023Department of Electrical and Computer Engineering, UCSB, Santa Barbara, CA, USADepartment of Electrical and Computer Engineering, UCSB, Santa Barbara, CA, USADepartment of Electrical and Computer Engineering, UCSB, Santa Barbara, CA, USAIntrinsically random hardware devices are increasingly attracting attention for their potential use in probabilistic computing architectures. One such device is the single-photon avalanche diode (SPAD) and an associated functional unit, the variable-rate SPAD circuit (VRSC), recently proposed by us as a source of randomness for sampling and annealing Ising and Potts models. This work develops a more advanced understanding of these VRSCs by introducing several VRSC design options and studying their tradeoffs as implemented in a 65-nm CMOS process. Each VRSC is composed of a SPAD and a processing circuit. Combinations of three different SPAD designs and three different types of processing circuits were evaluated on several metrics such as area, speed, and variability. Measured results from the SPAD design space show that even extremely small SPADs are suitable for probabilistic computing purposes, and that high dark count rates are not detrimental either, so SPADs for probabilistic computing are actually easier to integrate in standard CMOS processes. Results from the circuit design space show that the time-to-analog-based designs introduced in this work can produce highly exponential and analytical transfer functions, but that the less analytically tractable output of the previously proposed filter-based designs can achieve less variability in a smaller footprint. Probabilistic bits (P-bits) composed of the fabricated VRSCs achieve bit flip rates of 50 MHz and allow at least one order of magnitude of control over their simulated annealing temperature.https://ieeexplore.ieee.org/document/10659028/IsingoptimizationPottsprobabilisticprobabilistic bit (P-bit)single-photon avalanche diode (SPAD)
spellingShingle William Whitehead
Wonsik Oh
Luke Theogarajan
CMOS Single-Photon Avalanche Diode Circuits for Probabilistic Computing
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Ising
optimization
Potts
probabilistic
probabilistic bit (P-bit)
single-photon avalanche diode (SPAD)
title CMOS Single-Photon Avalanche Diode Circuits for Probabilistic Computing
title_full CMOS Single-Photon Avalanche Diode Circuits for Probabilistic Computing
title_fullStr CMOS Single-Photon Avalanche Diode Circuits for Probabilistic Computing
title_full_unstemmed CMOS Single-Photon Avalanche Diode Circuits for Probabilistic Computing
title_short CMOS Single-Photon Avalanche Diode Circuits for Probabilistic Computing
title_sort cmos single photon avalanche diode circuits for probabilistic computing
topic Ising
optimization
Potts
probabilistic
probabilistic bit (P-bit)
single-photon avalanche diode (SPAD)
url https://ieeexplore.ieee.org/document/10659028/
work_keys_str_mv AT williamwhitehead cmossinglephotonavalanchediodecircuitsforprobabilisticcomputing
AT wonsikoh cmossinglephotonavalanchediodecircuitsforprobabilisticcomputing
AT luketheogarajan cmossinglephotonavalanchediodecircuitsforprobabilisticcomputing