APEIRON: A framework for the development of smart TDAQ systems
APEIRON is a framework encompassing the general architecture of a distributed heterogeneous processing platform and the corresponding software stack, from the low level device drivers up to the high level programming model. Developers can define scalable applications that can be deployed on a multi-...
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| Main Authors: | , , , , , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
EDP Sciences
2025-01-01
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| Series: | EPJ Web of Conferences |
| Online Access: | https://www.epj-conferences.org/articles/epjconf/pdf/2025/04/epjconf_ricap2024_12013.pdf |
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| _version_ | 1849737124772839424 |
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| author | Ammendola Roberto Biagioni Andrea Chiarini Carlotta Ciardiello Andrea Cretaro Paolo Frezza Ottorino Lo Cicero Francesca Lonardo Alessandro Martinelli Michele Paolucci Pier Stanislao Perticaroli Pierpaolo Pontisso Luca Simula Francesco Rossi Cristian Vicini Piero |
| author_facet | Ammendola Roberto Biagioni Andrea Chiarini Carlotta Ciardiello Andrea Cretaro Paolo Frezza Ottorino Lo Cicero Francesca Lonardo Alessandro Martinelli Michele Paolucci Pier Stanislao Perticaroli Pierpaolo Pontisso Luca Simula Francesco Rossi Cristian Vicini Piero |
| author_sort | Ammendola Roberto |
| collection | DOAJ |
| description | APEIRON is a framework encompassing the general architecture of a distributed heterogeneous processing platform and the corresponding software stack, from the low level device drivers up to the high level programming model. Developers can define scalable applications that can be deployed on a multi-FPGA system coding at high level: the APEIRON communication IPs allow low-latency communication between processing tasks deployed on FPGAs, even if hosted on different computing nodes. Thanks to the use of High Level Synthesis tools, tasks are described in high level language (C/C++) while communication is expressed through a lightweight API. The aim of the APEIRON project was to develop a flexible framework that could be adopted in the design and implementation of both “traditional” low level trigger systems and of data reduction stages in trigger-less or streaming readout experimental setups. |
| format | Article |
| id | doaj-art-d9a655e674404c60ab902ddbbddcd894 |
| institution | DOAJ |
| issn | 2100-014X |
| language | English |
| publishDate | 2025-01-01 |
| publisher | EDP Sciences |
| record_format | Article |
| series | EPJ Web of Conferences |
| spelling | doaj-art-d9a655e674404c60ab902ddbbddcd8942025-08-20T03:07:02ZengEDP SciencesEPJ Web of Conferences2100-014X2025-01-013191201310.1051/epjconf/202531912013epjconf_ricap2024_12013APEIRON: A framework for the development of smart TDAQ systemsAmmendola Roberto0Biagioni Andrea1Chiarini Carlotta2Ciardiello Andrea3Cretaro Paolo4Frezza Ottorino5Lo Cicero Francesca6Lonardo Alessandro7Martinelli Michele8Paolucci Pier Stanislao9Perticaroli Pierpaolo10Pontisso Luca11Simula Francesco12Rossi Cristian13Vicini Piero14Istituto Nazionale di Fisica Nucleare (INFN), Sezione di Roma Tor VergataIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Superiore di SanitàIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaIstituto Nazionale di Fisica Nucleare (INFN), Sezione di RomaAPEIRON is a framework encompassing the general architecture of a distributed heterogeneous processing platform and the corresponding software stack, from the low level device drivers up to the high level programming model. Developers can define scalable applications that can be deployed on a multi-FPGA system coding at high level: the APEIRON communication IPs allow low-latency communication between processing tasks deployed on FPGAs, even if hosted on different computing nodes. Thanks to the use of High Level Synthesis tools, tasks are described in high level language (C/C++) while communication is expressed through a lightweight API. The aim of the APEIRON project was to develop a flexible framework that could be adopted in the design and implementation of both “traditional” low level trigger systems and of data reduction stages in trigger-less or streaming readout experimental setups.https://www.epj-conferences.org/articles/epjconf/pdf/2025/04/epjconf_ricap2024_12013.pdf |
| spellingShingle | Ammendola Roberto Biagioni Andrea Chiarini Carlotta Ciardiello Andrea Cretaro Paolo Frezza Ottorino Lo Cicero Francesca Lonardo Alessandro Martinelli Michele Paolucci Pier Stanislao Perticaroli Pierpaolo Pontisso Luca Simula Francesco Rossi Cristian Vicini Piero APEIRON: A framework for the development of smart TDAQ systems EPJ Web of Conferences |
| title | APEIRON: A framework for the development of smart TDAQ systems |
| title_full | APEIRON: A framework for the development of smart TDAQ systems |
| title_fullStr | APEIRON: A framework for the development of smart TDAQ systems |
| title_full_unstemmed | APEIRON: A framework for the development of smart TDAQ systems |
| title_short | APEIRON: A framework for the development of smart TDAQ systems |
| title_sort | apeiron a framework for the development of smart tdaq systems |
| url | https://www.epj-conferences.org/articles/epjconf/pdf/2025/04/epjconf_ricap2024_12013.pdf |
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