Redesigning CMOS VLSI using Yosys synthesis tool

Redesigning CMOS VLSI using Yosys synthesis tool

Objectives. The problem of reverse engineering of a transistor level circuit specified in the SPICE format in a different technological basis is considered. The goal of the work is to develop an approach to redesigning circuits using open source design automation software packages.Methods. A method...

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Bibliographic Details
Main Authors: D. I. Cheremisinov, L. D. Cheremisinova
Format: Article
Language:Russian
Published: National Academy of Sciences of Belarus, the United Institute of Informatics Problems 2025-03-01
Series:Informatika
Subjects:
reverse engineering, decompilation of transistor circuits, cmos circuits, spice format, language verilog, package yosys
Online Access:https://inf.grid.by/jour/article/view/1326
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