Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits
A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
1992-01-01
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| Series: | Active and Passive Electronic Components |
| Online Access: | http://dx.doi.org/10.1155/1992/13545 |
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