Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits
A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
1992-01-01
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| Series: | Active and Passive Electronic Components |
| Online Access: | http://dx.doi.org/10.1155/1992/13545 |
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| _version_ | 1849472859096743936 |
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| author | K. Z. Dimopoulos J. N. Avaritsiotis S. J. White |
| author_facet | K. Z. Dimopoulos J. N. Avaritsiotis S. J. White |
| author_sort | K. Z. Dimopoulos |
| collection | DOAJ |
| description | A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip
interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to
analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to
simulate the pulse propagation characteristics in high-speed integrated circuits. First the capacitance,
inductance, conductance and resistance matrices per unit length for the given multiconductor geometry
is computed. A multiple coupled line model consisting of uncoupled lossy transmission lines and linear
dependent current and voltage sources if finally calculated according to the capacitance, inductance,
conductance and resistance matrix values computed. |
| format | Article |
| id | doaj-art-d8fa17dc03fc4292bbbe4b8bb89781e2 |
| institution | Kabale University |
| issn | 0882-7516 1563-5031 |
| language | English |
| publishDate | 1992-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Active and Passive Electronic Components |
| spelling | doaj-art-d8fa17dc03fc4292bbbe4b8bb89781e22025-08-20T03:24:22ZengWileyActive and Passive Electronic Components0882-75161563-50311992-01-0114419921810.1155/1992/13545Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated CircuitsK. Z. Dimopoulos0J. N. Avaritsiotis1S. J. White2National Technical University of Athens, Dep. of Electrical Engineering, Div. of Computer Science, Zographou, Athens GR-15773, GreeceNational Technical University of Athens, Dep. of Electrical Engineering, Div. of Computer Science, Zographou, Athens GR-15773, GreeceGEC-Plessey Semiconductors, Tamerton Road, Roborough, Devon, Plymouth PL6 7BQ, UKA method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to simulate the pulse propagation characteristics in high-speed integrated circuits. First the capacitance, inductance, conductance and resistance matrices per unit length for the given multiconductor geometry is computed. A multiple coupled line model consisting of uncoupled lossy transmission lines and linear dependent current and voltage sources if finally calculated according to the capacitance, inductance, conductance and resistance matrix values computed.http://dx.doi.org/10.1155/1992/13545 |
| spellingShingle | K. Z. Dimopoulos J. N. Avaritsiotis S. J. White Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits Active and Passive Electronic Components |
| title | Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits |
| title_full | Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits |
| title_fullStr | Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits |
| title_full_unstemmed | Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits |
| title_short | Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits |
| title_sort | electrical modelling of multilevel on chip interconnections for high speed integrated circuits |
| url | http://dx.doi.org/10.1155/1992/13545 |
| work_keys_str_mv | AT kzdimopoulos electricalmodellingofmultilevelonchipinterconnectionsforhighspeedintegratedcircuits AT jnavaritsiotis electricalmodellingofmultilevelonchipinterconnectionsforhighspeedintegratedcircuits AT sjwhite electricalmodellingofmultilevelonchipinterconnectionsforhighspeedintegratedcircuits |