APA (7th ed.) Citation

Dimopoulos, K. Z., Avaritsiotis, J. N., & White, S. J. Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits. Wiley.

Chicago Style (17th ed.) Citation

Dimopoulos, K. Z., J. N. Avaritsiotis, and S. J. White. Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits. Wiley.

MLA (9th ed.) Citation

Dimopoulos, K. Z., et al. Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits. Wiley.