A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices
The introduction of Software-Defined Networking (SDN) separated the control and data forwarding planes, but the data plane still requires a fully programmable packet scheduler that can adapt to different traffic patterns and offer high expressiveness at line rate. The Dynamic Ranking Push-In-First-O...
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IEEE
2023-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10153594/ |
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| author | Mostafa Elbediwy Bill Pontikakis Jean-Pierre David Yvon Savaria |
| author_facet | Mostafa Elbediwy Bill Pontikakis Jean-Pierre David Yvon Savaria |
| author_sort | Mostafa Elbediwy |
| collection | DOAJ |
| description | The introduction of Software-Defined Networking (SDN) separated the control and data forwarding planes, but the data plane still requires a fully programmable packet scheduler that can adapt to different traffic patterns and offer high expressiveness at line rate. The Dynamic Ranking Push-In-First-Out (DR-PIFO) is a novel programmable hardware queue architecture, introduced for the widely-used Portable Switch Architecture (PSA) used in modern network switches and routers. With the aid of a re-ranking mechanism, the DR-PIFO offers a flexible and expressive solution for a wide range of scheduling algorithms while still meeting line rate requirements. Our design, synthesized using TSMC’s 65nm technology, achieves the desired timing rate of 1GHz while maintaining a throughput that matches the fastest existing schedulers and incurs a mere 15.5% increase in area compared to the state-of-the-art PIFO design. The proposed DR-PIFO’s hardware implementation is shown to closely approach the behavior and performance of its algorithmic model by efficiently executing various scheduling algorithms, leading to precise bandwidth distribution among traffic flows. Additionally, the DR-PIFO offers a significant reduction in the relative flow completion time (FCT) errors, exhibiting a minimum of 30% less error compared to the previously proposed models when implementing various scheduling policies with workloads collected from data centers. Thus, we believe that the DR-PIFO is a significant step toward making hardware packet schedulers more programmable. |
| format | Article |
| id | doaj-art-d5fff7265c15475d8ab94d875c4ddb7f |
| institution | DOAJ |
| issn | 2169-3536 |
| language | English |
| publishDate | 2023-01-01 |
| publisher | IEEE |
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| series | IEEE Access |
| spelling | doaj-art-d5fff7265c15475d8ab94d875c4ddb7f2025-08-20T03:10:31ZengIEEEIEEE Access2169-35362023-01-0111614226143610.1109/ACCESS.2023.328672610153594A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network DevicesMostafa Elbediwy0https://orcid.org/0000-0001-5073-510XBill Pontikakis1https://orcid.org/0009-0001-5074-3473Jean-Pierre David2https://orcid.org/0000-0002-7707-0483Yvon Savaria3https://orcid.org/0000-0002-3404-9959Department of Electrical Engineering, Polytechnique Montréal, Montreal, QC, CanadaDepartment of Electrical Engineering, Polytechnique Montréal, Montreal, QC, CanadaDepartment of Electrical Engineering, Polytechnique Montréal, Montreal, QC, CanadaDepartment of Electrical Engineering, Polytechnique Montréal, Montreal, QC, CanadaThe introduction of Software-Defined Networking (SDN) separated the control and data forwarding planes, but the data plane still requires a fully programmable packet scheduler that can adapt to different traffic patterns and offer high expressiveness at line rate. The Dynamic Ranking Push-In-First-Out (DR-PIFO) is a novel programmable hardware queue architecture, introduced for the widely-used Portable Switch Architecture (PSA) used in modern network switches and routers. With the aid of a re-ranking mechanism, the DR-PIFO offers a flexible and expressive solution for a wide range of scheduling algorithms while still meeting line rate requirements. Our design, synthesized using TSMC’s 65nm technology, achieves the desired timing rate of 1GHz while maintaining a throughput that matches the fastest existing schedulers and incurs a mere 15.5% increase in area compared to the state-of-the-art PIFO design. The proposed DR-PIFO’s hardware implementation is shown to closely approach the behavior and performance of its algorithmic model by efficiently executing various scheduling algorithms, leading to precise bandwidth distribution among traffic flows. Additionally, the DR-PIFO offers a significant reduction in the relative flow completion time (FCT) errors, exhibiting a minimum of 30% less error compared to the previously proposed models when implementing various scheduling policies with workloads collected from data centers. Thus, we believe that the DR-PIFO is a significant step toward making hardware packet schedulers more programmable.https://ieeexplore.ieee.org/document/10153594/Software-defined networkingprogrammable packet schedulershardware queuestraffic management |
| spellingShingle | Mostafa Elbediwy Bill Pontikakis Jean-Pierre David Yvon Savaria A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices IEEE Access Software-defined networking programmable packet schedulers hardware queues traffic management |
| title | A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices |
| title_full | A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices |
| title_fullStr | A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices |
| title_full_unstemmed | A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices |
| title_short | A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices |
| title_sort | hardware architecture of a dynamic ranking packet scheduler for programmable network devices |
| topic | Software-defined networking programmable packet schedulers hardware queues traffic management |
| url | https://ieeexplore.ieee.org/document/10153594/ |
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