A Dual-Mode Compatible CT ADC With FIR DAC and SB Quantization for DSM and IDSM Operations
This paper presents a continuous-time (CT) ADC capable of operating as either a delta-sigma modulator (DSM) or an incremental DSM (IDSM). To address the high jitter sensitivity inherent to oversampled CT systems, an architecture incorporating FIR DACs and a single-bit (SB) quantizer is adopted. A fu...
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2025-01-01
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| author | Han Yang Yuqi Wang Ying Hou Xiaosong Wang Yu Liu |
| author_facet | Han Yang Yuqi Wang Ying Hou Xiaosong Wang Yu Liu |
| author_sort | Han Yang |
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| description | This paper presents a continuous-time (CT) ADC capable of operating as either a delta-sigma modulator (DSM) or an incremental DSM (IDSM). To address the high jitter sensitivity inherent to oversampled CT systems, an architecture incorporating FIR DACs and a single-bit (SB) quantizer is adopted. A fully numerical loop parameter extraction method based on the least-mean-square (LMS) algorithm is proposed, eliminating the need for tedious algebraic derivations required in conventional approaches. Additionally, a multirate state-space simulation framework is introduced to address compatibility issues arising from excess loop delay (ELD), which conventional approaches fail to adequately handle. At the circuit level, a compact and energy-efficient compensation FIR DAC is implemented based on a configurable capacitive passive summation network. The main FIR DAC with 8 taps employs a Zapped Virtual-Ground-Switched Dual Return-To-Open (DRTO) topology to suppress ISI and the effects of limited reference impedance. Layout asymmetry in the main FIR DAC induces differential-mode (DM) crosstalk, which is alleviated through a layout-level cancellation technique leveraging even-indexed FIR taps. The prototype, fabricated in a TSMC 65 nm LP CMOS process with a core area of 0.235 mm2, achieves SNDRpeak of 84.3 dB and 81.3 dB in DSM and IDSM modes, respectively, over a 100 kHz bandwidth. Powered by a single 1.2 V supply, it consumes <inline-formula> <tex-math notation="LaTeX">$269~\mu $ </tex-math></inline-formula>W and <inline-formula> <tex-math notation="LaTeX">$277~\mu $ </tex-math></inline-formula>W in DSM and IDSM modes, corresponding to FoMSNDR of 170 dB and 166.9 dB. |
| format | Article |
| id | doaj-art-d41d9a71e2c64eb8b42ecc775686df18 |
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| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
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| spelling | doaj-art-d41d9a71e2c64eb8b42ecc775686df182025-08-20T03:12:27ZengIEEEIEEE Access2169-35362025-01-011311838111839310.1109/ACCESS.2025.358536311062919A Dual-Mode Compatible CT ADC With FIR DAC and SB Quantization for DSM and IDSM OperationsHan Yang0https://orcid.org/0009-0003-3232-910XYuqi Wang1https://orcid.org/0009-0007-7862-2570Ying Hou2https://orcid.org/0000-0003-4820-5438Xiaosong Wang3https://orcid.org/0000-0002-4653-4855Yu Liu4https://orcid.org/0000-0002-8417-6913Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, ChinaInstitute of Microelectronics of the Chinese Academy of Sciences, Beijing, ChinaInstitute of Microelectronics of the Chinese Academy of Sciences, Beijing, ChinaInstitute of Microelectronics of the Chinese Academy of Sciences, Beijing, ChinaInstitute of Microelectronics of the Chinese Academy of Sciences, Beijing, ChinaThis paper presents a continuous-time (CT) ADC capable of operating as either a delta-sigma modulator (DSM) or an incremental DSM (IDSM). To address the high jitter sensitivity inherent to oversampled CT systems, an architecture incorporating FIR DACs and a single-bit (SB) quantizer is adopted. A fully numerical loop parameter extraction method based on the least-mean-square (LMS) algorithm is proposed, eliminating the need for tedious algebraic derivations required in conventional approaches. Additionally, a multirate state-space simulation framework is introduced to address compatibility issues arising from excess loop delay (ELD), which conventional approaches fail to adequately handle. At the circuit level, a compact and energy-efficient compensation FIR DAC is implemented based on a configurable capacitive passive summation network. The main FIR DAC with 8 taps employs a Zapped Virtual-Ground-Switched Dual Return-To-Open (DRTO) topology to suppress ISI and the effects of limited reference impedance. Layout asymmetry in the main FIR DAC induces differential-mode (DM) crosstalk, which is alleviated through a layout-level cancellation technique leveraging even-indexed FIR taps. The prototype, fabricated in a TSMC 65 nm LP CMOS process with a core area of 0.235 mm2, achieves SNDRpeak of 84.3 dB and 81.3 dB in DSM and IDSM modes, respectively, over a 100 kHz bandwidth. Powered by a single 1.2 V supply, it consumes <inline-formula> <tex-math notation="LaTeX">$269~\mu $ </tex-math></inline-formula>W and <inline-formula> <tex-math notation="LaTeX">$277~\mu $ </tex-math></inline-formula>W in DSM and IDSM modes, corresponding to FoMSNDR of 170 dB and 166.9 dB.https://ieeexplore.ieee.org/document/11062919/CT-ADCDSMincrementalFIR DACLMSstate-space |
| spellingShingle | Han Yang Yuqi Wang Ying Hou Xiaosong Wang Yu Liu A Dual-Mode Compatible CT ADC With FIR DAC and SB Quantization for DSM and IDSM Operations IEEE Access CT-ADC DSM incremental FIR DAC LMS state-space |
| title | A Dual-Mode Compatible CT ADC With FIR DAC and SB Quantization for DSM and IDSM Operations |
| title_full | A Dual-Mode Compatible CT ADC With FIR DAC and SB Quantization for DSM and IDSM Operations |
| title_fullStr | A Dual-Mode Compatible CT ADC With FIR DAC and SB Quantization for DSM and IDSM Operations |
| title_full_unstemmed | A Dual-Mode Compatible CT ADC With FIR DAC and SB Quantization for DSM and IDSM Operations |
| title_short | A Dual-Mode Compatible CT ADC With FIR DAC and SB Quantization for DSM and IDSM Operations |
| title_sort | dual mode compatible ct adc with fir dac and sb quantization for dsm and idsm operations |
| topic | CT-ADC DSM incremental FIR DAC LMS state-space |
| url | https://ieeexplore.ieee.org/document/11062919/ |
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