Design of a fast-acquisition phase-locked loop for frequency control systems
Phase-locked loop (PLL) is a negative feedback control system that can achieve phase synchronization of two signals. Its filtering effect can make its passband narrow, and its output frequency automatically track the input frequency. Phase locked loops are often used in atomic clocks, frequency stan...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2024-02-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000163489 |
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| Summary: | Phase-locked loop (PLL) is a negative feedback control system that can achieve phase synchronization of two signals. Its filtering effect can make its passband narrow, and its output frequency automatically track the input frequency. Phase locked loops are often used in atomic clocks, frequency standard taming systems, and time synchronization systems. PLL is an important component of communication, satellite navigation, and electrical measurement systems. Phase noise and acquisition time are two mutually constraining indicators in a PLL. Reducing the frequency acquisition time of a PLL while suppressing phase noise is one of the important issues in current research on phase-lock techniques. To solve this problem, this paper designs an auxiliary acquisition circuit based on the basic theory and composition of analog PLL and the mathematical relationship between loop bandwidth and acquisition time. |
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| ISSN: | 0258-7998 |