The Design of a Low-Power Pipelined ADC for IoT Applications
This paper proposes a low-power 10-bit 20 MS/s pipelined analog-to-digital converter (ADC) designed for the burgeoning needs of low-data-rate communication systems, particularly within the Internet of Things (IoT) domain. To reduce power usage, multiple power-saving techniques are combined, such as...
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MDPI AG
2025-02-01
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| Online Access: | https://www.mdpi.com/1424-8220/25/5/1343 |
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| author | Junkai Zhang Tao Sun Zunkai Huang Wei Tao Ning Wang Li Tian Yongxin Zhu Hui Wang |
| author_facet | Junkai Zhang Tao Sun Zunkai Huang Wei Tao Ning Wang Li Tian Yongxin Zhu Hui Wang |
| author_sort | Junkai Zhang |
| collection | DOAJ |
| description | This paper proposes a low-power 10-bit 20 MS/s pipelined analog-to-digital converter (ADC) designed for the burgeoning needs of low-data-rate communication systems, particularly within the Internet of Things (IoT) domain. To reduce power usage, multiple power-saving techniques are combined, such as sample-and-hold amplifier-less (SHA-less) architecture, capacitor scaling, and dynamic comparators. In addition, this paper presents a novel operational amplifier (op-amp) with gain boosting, featuring a dual-input differential pair that enables internal pipeline stage switching, effectively alleviating the crosstalk and memory effects inherent in conventional shared op-amp configurations, thereby further reducing power consumption. A prototype ADC was fabricated in a 180 nm CMOS process and the core size was 0.333 mm<sup>2</sup>. The ADC implemented operated at a 20 MHz sampling rate under a 1.8 V supply voltage. It achieved a spurious-free dynamic range (SFDR) of 61.83 dB and a signal-to-noise-and-distortion ratio (SNDR) of 54.15 dB while demonstrating a maximum differential non-linearity (DNL) of 0.36 least significant bit (LSB) and a maximum integral non-linearity (INL) of 0.67 LSB. Notably, the ADC consumed less than 5 mW of power at the mentioned sampling frequency, showcasing excellent power efficiency. |
| format | Article |
| id | doaj-art-d28985d17de242ec8a52e627f2889310 |
| institution | DOAJ |
| issn | 1424-8220 |
| language | English |
| publishDate | 2025-02-01 |
| publisher | MDPI AG |
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| series | Sensors |
| spelling | doaj-art-d28985d17de242ec8a52e627f28893102025-08-20T02:59:01ZengMDPI AGSensors1424-82202025-02-01255134310.3390/s25051343The Design of a Low-Power Pipelined ADC for IoT ApplicationsJunkai Zhang0Tao Sun1Zunkai Huang2Wei Tao3Ning Wang4Li Tian5Yongxin Zhu6Hui Wang7Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201210, ChinaSynopsys Semiconductor Technology (Shanghai) Co., Ltd., Shanghai 200433, ChinaShanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201210, ChinaShanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201210, ChinaShanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201210, ChinaShanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201210, ChinaShanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201210, ChinaShanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201210, ChinaThis paper proposes a low-power 10-bit 20 MS/s pipelined analog-to-digital converter (ADC) designed for the burgeoning needs of low-data-rate communication systems, particularly within the Internet of Things (IoT) domain. To reduce power usage, multiple power-saving techniques are combined, such as sample-and-hold amplifier-less (SHA-less) architecture, capacitor scaling, and dynamic comparators. In addition, this paper presents a novel operational amplifier (op-amp) with gain boosting, featuring a dual-input differential pair that enables internal pipeline stage switching, effectively alleviating the crosstalk and memory effects inherent in conventional shared op-amp configurations, thereby further reducing power consumption. A prototype ADC was fabricated in a 180 nm CMOS process and the core size was 0.333 mm<sup>2</sup>. The ADC implemented operated at a 20 MHz sampling rate under a 1.8 V supply voltage. It achieved a spurious-free dynamic range (SFDR) of 61.83 dB and a signal-to-noise-and-distortion ratio (SNDR) of 54.15 dB while demonstrating a maximum differential non-linearity (DNL) of 0.36 least significant bit (LSB) and a maximum integral non-linearity (INL) of 0.67 LSB. Notably, the ADC consumed less than 5 mW of power at the mentioned sampling frequency, showcasing excellent power efficiency.https://www.mdpi.com/1424-8220/25/5/1343pipelined analog-to-digital converter (ADC)low powersample-and-hold amplifier-less (SHA-less)op-amp sharing |
| spellingShingle | Junkai Zhang Tao Sun Zunkai Huang Wei Tao Ning Wang Li Tian Yongxin Zhu Hui Wang The Design of a Low-Power Pipelined ADC for IoT Applications Sensors pipelined analog-to-digital converter (ADC) low power sample-and-hold amplifier-less (SHA-less) op-amp sharing |
| title | The Design of a Low-Power Pipelined ADC for IoT Applications |
| title_full | The Design of a Low-Power Pipelined ADC for IoT Applications |
| title_fullStr | The Design of a Low-Power Pipelined ADC for IoT Applications |
| title_full_unstemmed | The Design of a Low-Power Pipelined ADC for IoT Applications |
| title_short | The Design of a Low-Power Pipelined ADC for IoT Applications |
| title_sort | design of a low power pipelined adc for iot applications |
| topic | pipelined analog-to-digital converter (ADC) low power sample-and-hold amplifier-less (SHA-less) op-amp sharing |
| url | https://www.mdpi.com/1424-8220/25/5/1343 |
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