A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction
This paper presents the design of a 10 GHz dual-loop PLL with active cycle-jitter correction. In the main loop of the PLL, a sampling PD is utilized to suppress the in-band noise to reach the reference noise floor. On the other hand, to eliminate noise disturbance outside the PLL loop bandwidth, an...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
|
| Series: | IEEE Open Journal of Circuits and Systems |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10561565/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832592892811542528 |
|---|---|
| author | Yu-Ping Huang Yu-Sian Lu Wei-Zen Chen |
| author_facet | Yu-Ping Huang Yu-Sian Lu Wei-Zen Chen |
| author_sort | Yu-Ping Huang |
| collection | DOAJ |
| description | This paper presents the design of a 10 GHz dual-loop PLL with active cycle-jitter correction. In the main loop of the PLL, a sampling PD is utilized to suppress the in-band noise to reach the reference noise floor. On the other hand, to eliminate noise disturbance outside the PLL loop bandwidth, an active cycle-jitter correction (ACJC) loop is proposed and incorporated in this design. The ACJC utilizes a delay-discriminator based cycle jitter extractor and is performed at the subharmonic of VCO. It provides jitter suppression far beyond a conventional PLL loop bandwidth. An experimental prototype has been fabricated in a TSMC 40 nm CMOS process. By activating the ACJC, the spurious tones can be reduced by 12 dB when a 260MHz disturbance is injected without resort to sophisticated calibration. The integrated jitter from 1kHz to 260 MHz can be reduced from 413.7 fs to 293.21 fs, which corresponds to 29% improvement in jitter reduction. The PLL core consumes 22.1 mW. The chip area is about 0.97x0.96 mm2. |
| format | Article |
| id | doaj-art-d158e1028eef405081353b430a87cc17 |
| institution | Kabale University |
| issn | 2644-1225 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj-art-d158e1028eef405081353b430a87cc172025-01-21T00:02:53ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252024-01-01529130110.1109/OJCAS.2024.341639710561565A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter ReductionYu-Ping Huang0https://orcid.org/0000-0002-8599-2883Yu-Sian Lu1Wei-Zen Chen2https://orcid.org/0000-0001-5126-9163Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, TaiwanInstitute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, TaiwanInstitute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, TaiwanThis paper presents the design of a 10 GHz dual-loop PLL with active cycle-jitter correction. In the main loop of the PLL, a sampling PD is utilized to suppress the in-band noise to reach the reference noise floor. On the other hand, to eliminate noise disturbance outside the PLL loop bandwidth, an active cycle-jitter correction (ACJC) loop is proposed and incorporated in this design. The ACJC utilizes a delay-discriminator based cycle jitter extractor and is performed at the subharmonic of VCO. It provides jitter suppression far beyond a conventional PLL loop bandwidth. An experimental prototype has been fabricated in a TSMC 40 nm CMOS process. By activating the ACJC, the spurious tones can be reduced by 12 dB when a 260MHz disturbance is injected without resort to sophisticated calibration. The integrated jitter from 1kHz to 260 MHz can be reduced from 413.7 fs to 293.21 fs, which corresponds to 29% improvement in jitter reduction. The PLL core consumes 22.1 mW. The chip area is about 0.97x0.96 mm2.https://ieeexplore.ieee.org/document/10561565/Sampling-based PD (SPD)sub-sampling PD (SSPD)active cycle-jitter correction (ACJC) |
| spellingShingle | Yu-Ping Huang Yu-Sian Lu Wei-Zen Chen A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction IEEE Open Journal of Circuits and Systems Sampling-based PD (SPD) sub-sampling PD (SSPD) active cycle-jitter correction (ACJC) |
| title | A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction |
| title_full | A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction |
| title_fullStr | A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction |
| title_full_unstemmed | A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction |
| title_short | A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction |
| title_sort | 10 ghz dual loop pll with active cycle jitter correction achieving 12db spur and 29 jitter reduction |
| topic | Sampling-based PD (SPD) sub-sampling PD (SSPD) active cycle-jitter correction (ACJC) |
| url | https://ieeexplore.ieee.org/document/10561565/ |
| work_keys_str_mv | AT yupinghuang a10ghzduallooppllwithactivecyclejittercorrectionachieving12dbspurand29jitterreduction AT yusianlu a10ghzduallooppllwithactivecyclejittercorrectionachieving12dbspurand29jitterreduction AT weizenchen a10ghzduallooppllwithactivecyclejittercorrectionachieving12dbspurand29jitterreduction AT yupinghuang 10ghzduallooppllwithactivecyclejittercorrectionachieving12dbspurand29jitterreduction AT yusianlu 10ghzduallooppllwithactivecyclejittercorrectionachieving12dbspurand29jitterreduction AT weizenchen 10ghzduallooppllwithactivecyclejittercorrectionachieving12dbspurand29jitterreduction |