Ultra-small Hysteresis IGZO Thin-Film Transistors with Room-Temperature Sputtered SiO2 as Dielectric Layer
A sputtered silicon dioxide dielectric is prepared for fabrication of indium gallium zinc oxide (IGZO) thin-film transistors (TFTs). We analyzed the dependence of device characteristics on gate voltage range. Clockwise hysteresis occurs at a low gate voltage ( Vgs ≤ 3 V) due to oxide traps near the...
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Tamkang University Press
2025-03-01
|
| Series: | Journal of Applied Science and Engineering |
| Subjects: | |
| Online Access: | http://jase.tku.edu.tw/articles/jase-202510-28-10-0011 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1849706777326649344 |
|---|---|
| author | Fangfei Han Zheng Lu Luan Fu Lulu Du Xiaohui Shi |
| author_facet | Fangfei Han Zheng Lu Luan Fu Lulu Du Xiaohui Shi |
| author_sort | Fangfei Han |
| collection | DOAJ |
| description | A sputtered silicon dioxide dielectric is prepared for fabrication of indium gallium zinc oxide (IGZO) thin-film
transistors (TFTs). We analyzed the dependence of device characteristics on gate voltage range. Clockwise hysteresis occurs at a low gate voltage ( Vgs ≤ 3 V) due to oxide traps near the SiO2/IGZO interface. At higher gate voltage ( Vgs = 5 V) a second, hysteresis collapse appears, which can be attributed to the coexistence of electron trapping and ion migration with a compatible and the opposite contributions to the hysteresis. Due to the dominant ion migration, hysteresis inversion (clockwise to anti-clockwise) appears at Vgs = 7 V. At Vgs = 10 V, devices performance degrades significantly, which may be ascribed to the electrochemical reaction. Further, a bias stress measurement indicates that the devices work effectively under a wide range Vgs of 1 ∼ 7 V |
| format | Article |
| id | doaj-art-ce695e67b4e244fa87bbf210889c7a09 |
| institution | DOAJ |
| issn | 2708-9967 2708-9975 |
| language | English |
| publishDate | 2025-03-01 |
| publisher | Tamkang University Press |
| record_format | Article |
| series | Journal of Applied Science and Engineering |
| spelling | doaj-art-ce695e67b4e244fa87bbf210889c7a092025-08-20T03:16:06ZengTamkang University PressJournal of Applied Science and Engineering2708-99672708-99752025-03-012810 1987199310.6180/jase.202510_28(10).0011Ultra-small Hysteresis IGZO Thin-Film Transistors with Room-Temperature Sputtered SiO2 as Dielectric LayerFangfei Han0Zheng Lu1Luan Fu2Lulu Du3Xiaohui Shi4School of Physics and Electronic Engineering, Linyi University, Linyi, 276000, ChinaSchool of Physics and Electronic Engineering, Linyi University, Linyi, 276000, ChinaSchool of Physics and Electronic Engineering, Linyi University, Linyi, 276000, ChinaSchool of Physics and Electronic Engineering, Linyi University, Linyi, 276000, ChinaSchool of Physics and Electronic Engineering, Linyi University, Linyi, 276000, ChinaA sputtered silicon dioxide dielectric is prepared for fabrication of indium gallium zinc oxide (IGZO) thin-film transistors (TFTs). We analyzed the dependence of device characteristics on gate voltage range. Clockwise hysteresis occurs at a low gate voltage ( Vgs ≤ 3 V) due to oxide traps near the SiO2/IGZO interface. At higher gate voltage ( Vgs = 5 V) a second, hysteresis collapse appears, which can be attributed to the coexistence of electron trapping and ion migration with a compatible and the opposite contributions to the hysteresis. Due to the dominant ion migration, hysteresis inversion (clockwise to anti-clockwise) appears at Vgs = 7 V. At Vgs = 10 V, devices performance degrades significantly, which may be ascribed to the electrochemical reaction. Further, a bias stress measurement indicates that the devices work effectively under a wide range Vgs of 1 ∼ 7 Vhttp://jase.tku.edu.tw/articles/jase-202510-28-10-0011indium gallium zinc oxide (igzo)thin-film transistors (tfts)hysteresissputtered sio2 |
| spellingShingle | Fangfei Han Zheng Lu Luan Fu Lulu Du Xiaohui Shi Ultra-small Hysteresis IGZO Thin-Film Transistors with Room-Temperature Sputtered SiO2 as Dielectric Layer Journal of Applied Science and Engineering indium gallium zinc oxide (igzo) thin-film transistors (tfts) hysteresis sputtered sio2 |
| title | Ultra-small Hysteresis IGZO Thin-Film Transistors with Room-Temperature Sputtered SiO2 as Dielectric Layer |
| title_full | Ultra-small Hysteresis IGZO Thin-Film Transistors with Room-Temperature Sputtered SiO2 as Dielectric Layer |
| title_fullStr | Ultra-small Hysteresis IGZO Thin-Film Transistors with Room-Temperature Sputtered SiO2 as Dielectric Layer |
| title_full_unstemmed | Ultra-small Hysteresis IGZO Thin-Film Transistors with Room-Temperature Sputtered SiO2 as Dielectric Layer |
| title_short | Ultra-small Hysteresis IGZO Thin-Film Transistors with Room-Temperature Sputtered SiO2 as Dielectric Layer |
| title_sort | ultra small hysteresis igzo thin film transistors with room temperature sputtered sio2 as dielectric layer |
| topic | indium gallium zinc oxide (igzo) thin-film transistors (tfts) hysteresis sputtered sio2 |
| url | http://jase.tku.edu.tw/articles/jase-202510-28-10-0011 |
| work_keys_str_mv | AT fangfeihan ultrasmallhysteresisigzothinfilmtransistorswithroomtemperaturesputteredsio2asdielectriclayer AT zhenglu ultrasmallhysteresisigzothinfilmtransistorswithroomtemperaturesputteredsio2asdielectriclayer AT luanfu ultrasmallhysteresisigzothinfilmtransistorswithroomtemperaturesputteredsio2asdielectriclayer AT luludu ultrasmallhysteresisigzothinfilmtransistorswithroomtemperaturesputteredsio2asdielectriclayer AT xiaohuishi ultrasmallhysteresisigzothinfilmtransistorswithroomtemperaturesputteredsio2asdielectriclayer |