High-Speed FPGA 10's Complement Adders-Subtractors
This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are pres...
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| Format: | Article |
| Language: | English |
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Wiley
2010-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2010/219764 |
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| author | G. Bioul M. Vazquez J. P. Deschamps G. Sutter |
| author_facet | G. Bioul M. Vazquez J. P. Deschamps G. Sutter |
| author_sort | G. Bioul |
| collection | DOAJ |
| description | This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are presented. Then, attention is given to FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 4-input LUTs (Virtex-4, Spartan-3) and 6-input LUTs (Virtex-5) Xilinx FPGA platforms. All designs are presented with the corresponding time performance and area consumption figures. Results have been compared to straight implementations of a decimal ripple-carry adder and an FPGA 2's complement binary adder-subtractor using the dedicated carry logic, both carried out on the same platform. Better time delays have been registered for decimal numbers within the same range of operands. |
| format | Article |
| id | doaj-art-ce3ca086116f49a3bc5f5efe950da152 |
| institution | OA Journals |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2010-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-ce3ca086116f49a3bc5f5efe950da1522025-08-20T02:19:30ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092010-01-01201010.1155/2010/219764219764High-Speed FPGA 10's Complement Adders-SubtractorsG. Bioul0M. Vazquez1J. P. Deschamps2G. Sutter3Faculty of System Engineering, FASTA University, Mar del Plata, ArgentinaFaculty of System Engineering, UNCPBA University, Tandil, ArgentinaFaculty of System Engineering, FASTA University, Mar del Plata, ArgentinaSchool of Engineering, Universidad Autónoma de Madrid, Madrid, SpainThis paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are presented. Then, attention is given to FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 4-input LUTs (Virtex-4, Spartan-3) and 6-input LUTs (Virtex-5) Xilinx FPGA platforms. All designs are presented with the corresponding time performance and area consumption figures. Results have been compared to straight implementations of a decimal ripple-carry adder and an FPGA 2's complement binary adder-subtractor using the dedicated carry logic, both carried out on the same platform. Better time delays have been registered for decimal numbers within the same range of operands.http://dx.doi.org/10.1155/2010/219764 |
| spellingShingle | G. Bioul M. Vazquez J. P. Deschamps G. Sutter High-Speed FPGA 10's Complement Adders-Subtractors International Journal of Reconfigurable Computing |
| title | High-Speed FPGA 10's Complement Adders-Subtractors |
| title_full | High-Speed FPGA 10's Complement Adders-Subtractors |
| title_fullStr | High-Speed FPGA 10's Complement Adders-Subtractors |
| title_full_unstemmed | High-Speed FPGA 10's Complement Adders-Subtractors |
| title_short | High-Speed FPGA 10's Complement Adders-Subtractors |
| title_sort | high speed fpga 10 s complement adders subtractors |
| url | http://dx.doi.org/10.1155/2010/219764 |
| work_keys_str_mv | AT gbioul highspeedfpga10scomplementadderssubtractors AT mvazquez highspeedfpga10scomplementadderssubtractors AT jpdeschamps highspeedfpga10scomplementadderssubtractors AT gsutter highspeedfpga10scomplementadderssubtractors |