Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System
Reservoir computing (RC) possesses a simple architecture and high energy efficiency for time‐series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoreg...
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| Format: | Article |
| Language: | English |
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Wiley
2024-10-01
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| Series: | Advanced Intelligent Systems |
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| Online Access: | https://doi.org/10.1002/aisy.202400098 |
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| author | Danian Dong Woyu Zhang Yuanlu Xie Jinshan Yue Kuan Ren Hongjian Huang Xu Zheng Wen Xuan Sun Jin Ru Lai Shaoyang Fan Hongzhou Wang Zhaoan Yu Zhihong Yao Xiaoxin Xu Dashan Shang Ming Liu |
| author_facet | Danian Dong Woyu Zhang Yuanlu Xie Jinshan Yue Kuan Ren Hongjian Huang Xu Zheng Wen Xuan Sun Jin Ru Lai Shaoyang Fan Hongzhou Wang Zhaoan Yu Zhihong Yao Xiaoxin Xu Dashan Shang Ming Liu |
| author_sort | Danian Dong |
| collection | DOAJ |
| description | Reservoir computing (RC) possesses a simple architecture and high energy efficiency for time‐series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoregression (NVAR) distinguishes itself due to its fewer hyperparameters and independence from physical random connection matrices, while yielding comparable results. However, NGRC networks struggle with massive Kronecker product calculations and matrix‐vector multiplications within the read out layer, leading to substantial efficiency challenges for traditional von Neumann architectures. In this work, a hybrid digital‐analog hardware system tailored for NGRC is developed. The digital part is a Kronecker product calculation unit with data filtering, which realizes transformation of nonlinear vector of the input linear vector. For matrix‐vector multiplication, a computing‐in‐memory architecture based on resistive random access memory array offers an energy‐efficient hardware solution, which markedly reduces data transfer and greatly improve computational parallelism and energy efficiency. The predictive capabilities of this hybrid NGRC system are validated through the Lorenz63 model, achieving a normalized root mean square error (NRMSE) of 0.00098 and an energy efficiency of 19.42TOPS W−1. |
| format | Article |
| id | doaj-art-ccf274fc05ba4f94bfb4dcb1dd3a1470 |
| institution | OA Journals |
| issn | 2640-4567 |
| language | English |
| publishDate | 2024-10-01 |
| publisher | Wiley |
| record_format | Article |
| series | Advanced Intelligent Systems |
| spelling | doaj-art-ccf274fc05ba4f94bfb4dcb1dd3a14702025-08-20T01:47:33ZengWileyAdvanced Intelligent Systems2640-45672024-10-01610n/an/a10.1002/aisy.202400098Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog SystemDanian Dong0Woyu Zhang1Yuanlu Xie2Jinshan Yue3Kuan Ren4Hongjian Huang5Xu Zheng6Wen Xuan Sun7Jin Ru Lai8Shaoyang Fan9Hongzhou Wang10Zhaoan Yu11Zhihong Yao12Xiaoxin Xu13Dashan Shang14Ming Liu15Laboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaLaboratory of Microelectronic Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 ChinaReservoir computing (RC) possesses a simple architecture and high energy efficiency for time‐series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoregression (NVAR) distinguishes itself due to its fewer hyperparameters and independence from physical random connection matrices, while yielding comparable results. However, NGRC networks struggle with massive Kronecker product calculations and matrix‐vector multiplications within the read out layer, leading to substantial efficiency challenges for traditional von Neumann architectures. In this work, a hybrid digital‐analog hardware system tailored for NGRC is developed. The digital part is a Kronecker product calculation unit with data filtering, which realizes transformation of nonlinear vector of the input linear vector. For matrix‐vector multiplication, a computing‐in‐memory architecture based on resistive random access memory array offers an energy‐efficient hardware solution, which markedly reduces data transfer and greatly improve computational parallelism and energy efficiency. The predictive capabilities of this hybrid NGRC system are validated through the Lorenz63 model, achieving a normalized root mean square error (NRMSE) of 0.00098 and an energy efficiency of 19.42TOPS W−1.https://doi.org/10.1002/aisy.202400098computing‐in‐memoryhybrid systemreservoir computingresistive random access memory |
| spellingShingle | Danian Dong Woyu Zhang Yuanlu Xie Jinshan Yue Kuan Ren Hongjian Huang Xu Zheng Wen Xuan Sun Jin Ru Lai Shaoyang Fan Hongzhou Wang Zhaoan Yu Zhihong Yao Xiaoxin Xu Dashan Shang Ming Liu Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System Advanced Intelligent Systems computing‐in‐memory hybrid system reservoir computing resistive random access memory |
| title | Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System |
| title_full | Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System |
| title_fullStr | Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System |
| title_full_unstemmed | Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System |
| title_short | Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System |
| title_sort | hardware implementation of next generation reservoir computing with rram based hybrid digital analog system |
| topic | computing‐in‐memory hybrid system reservoir computing resistive random access memory |
| url | https://doi.org/10.1002/aisy.202400098 |
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