Logical gates recognition in a flat transistor circuit
O b j e c t i v e s. With the increasing complexity of verification and simulation of modern VLSI, containing hundreds of millions of transistors, the means of extracting the hierarchical description at the level of logical elements froma flat description of circuits at the transistor level are beco...
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| Format: | Article |
| Language: | Russian |
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National Academy of Sciences of Belarus, the United Institute of Informatics Problems
2021-12-01
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| Series: | Informatika |
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| Online Access: | https://inf.grid.by/jour/article/view/1168 |
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| author | D. I. Cheremisinov L. D. Cheremisinova |
| author_facet | D. I. Cheremisinov L. D. Cheremisinova |
| author_sort | D. I. Cheremisinov |
| collection | DOAJ |
| description | O b j e c t i v e s. With the increasing complexity of verification and simulation of modern VLSI, containing hundreds of millions of transistors, the means of extracting the hierarchical description at the level of logical elements froma flat description of circuits at the transistor level are becoming the main tools for computer-aided design and verification. Decompilation tools for transistor circuits can not only significantly reduce the time to perform VLSI topology check, but also provide the basis for generating test cases, logical reengineering of integrated circuits and reverse engineering to detect untrusted attachments.The objective of the work is to solve the problem of extracting the structure of the functional level from a flat circuit of the transistor level by recognizing in it subcircuits that implement logical elements.M e t h o d s. Graph based methods are proposed for solving some key problems arising at the stage of structural recognition of CMOS gates in a transistor circuit: partitioning a graph into connectivity components corresponding to transistor subcircuits; recognition of subcircuits that are logical elements, and functions implemented by them; forming a library of recognized gates and constructing two-level transistor circuit. The original flat and resulting two-level transistor circuits are presented in SPICE format.Re s u l t s. The proposed methods are implemented in C++ as a part of a transistor circuit decompilation programfor the case without any predetermined cell library. All steps of the proposed methods of structural CMOS gates recognition are performed in a linear time from the number of transistors in the initial circuit.Co n c l u s i o n. The decompilation program has been tested on practical transistor-level circuits. Experiments indicate that the present tool is fast enough to process circuits with more than a hundred thousand transistors in a few minutes on a personal computer. Currently, the authors are developing methods for recognizing more complex elements in a transistor circuit, such as memory elements. |
| format | Article |
| id | doaj-art-caebc33c9a334e5ba346be8f41a13e0c |
| institution | Kabale University |
| issn | 1816-0301 |
| language | Russian |
| publishDate | 2021-12-01 |
| publisher | National Academy of Sciences of Belarus, the United Institute of Informatics Problems |
| record_format | Article |
| series | Informatika |
| spelling | doaj-art-caebc33c9a334e5ba346be8f41a13e0c2025-08-20T04:00:40ZrusNational Academy of Sciences of Belarus, the United Institute of Informatics ProblemsInformatika1816-03012021-12-011849610710.37661/1816-0301-2021-18-4-96-107985Logical gates recognition in a flat transistor circuitD. I. Cheremisinov0L. D. Cheremisinova1The United Institute of Informatics Problems of the National Academy of Sciences of BelarusThe United Institute of Informatics Problems of the National Academy of Sciences of BelarusO b j e c t i v e s. With the increasing complexity of verification and simulation of modern VLSI, containing hundreds of millions of transistors, the means of extracting the hierarchical description at the level of logical elements froma flat description of circuits at the transistor level are becoming the main tools for computer-aided design and verification. Decompilation tools for transistor circuits can not only significantly reduce the time to perform VLSI topology check, but also provide the basis for generating test cases, logical reengineering of integrated circuits and reverse engineering to detect untrusted attachments.The objective of the work is to solve the problem of extracting the structure of the functional level from a flat circuit of the transistor level by recognizing in it subcircuits that implement logical elements.M e t h o d s. Graph based methods are proposed for solving some key problems arising at the stage of structural recognition of CMOS gates in a transistor circuit: partitioning a graph into connectivity components corresponding to transistor subcircuits; recognition of subcircuits that are logical elements, and functions implemented by them; forming a library of recognized gates and constructing two-level transistor circuit. The original flat and resulting two-level transistor circuits are presented in SPICE format.Re s u l t s. The proposed methods are implemented in C++ as a part of a transistor circuit decompilation programfor the case without any predetermined cell library. All steps of the proposed methods of structural CMOS gates recognition are performed in a linear time from the number of transistors in the initial circuit.Co n c l u s i o n. The decompilation program has been tested on practical transistor-level circuits. Experiments indicate that the present tool is fast enough to process circuits with more than a hundred thousand transistors in a few minutes on a personal computer. Currently, the authors are developing methods for recognizing more complex elements in a transistor circuit, such as memory elements.https://inf.grid.by/jour/article/view/1168transistor subcircuit extractioncmos circuitsvlsi layout verificationvlsi reengineeringlogical gates recognitionspice format |
| spellingShingle | D. I. Cheremisinov L. D. Cheremisinova Logical gates recognition in a flat transistor circuit Informatika transistor subcircuit extraction cmos circuits vlsi layout verification vlsi reengineering logical gates recognition spice format |
| title | Logical gates recognition in a flat transistor circuit |
| title_full | Logical gates recognition in a flat transistor circuit |
| title_fullStr | Logical gates recognition in a flat transistor circuit |
| title_full_unstemmed | Logical gates recognition in a flat transistor circuit |
| title_short | Logical gates recognition in a flat transistor circuit |
| title_sort | logical gates recognition in a flat transistor circuit |
| topic | transistor subcircuit extraction cmos circuits vlsi layout verification vlsi reengineering logical gates recognition spice format |
| url | https://inf.grid.by/jour/article/view/1168 |
| work_keys_str_mv | AT dicheremisinov logicalgatesrecognitioninaflattransistorcircuit AT ldcheremisinova logicalgatesrecognitioninaflattransistorcircuit |