A 5-Gb/s 66 dB CMOS Variable-Gain Amplifier With Reconfigurable DC-Offset Cancellation for Multi-Standard Applications
This paper proposes a variable gain amplifier (VGA) with reconfigurable DC-offset cancellation (DCOC) for multi-standard applications. In this design, a cell-based design method and some bandwidth extension technologies are adopted to achieve a high data rate and a wide gain control range simultaneo...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2018-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8447188/ |
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| Summary: | This paper proposes a variable gain amplifier (VGA) with reconfigurable DC-offset cancellation (DCOC) for multi-standard applications. In this design, a cell-based design method and some bandwidth extension technologies are adopted to achieve a high data rate and a wide gain control range simultaneously. In addition, the DCOC having a tunable lower-cutoff frequency can make an optimum compromise between BER and SNR according to the specified baseband standard. The measurements show that the VGA achieves a gain control range from −6 dB to 60 dB, a bandwidth beyond 3 GHz, and a tunable lower-cutoff frequency from 0 to 300 kHz. When entering a 2<sup>23</sup>−1 pseudo-random bit sequence signal at 5 Gb/s, the VGA consumes 17 mW from a 1.2-V supply and the output data peak-to-peak jitter is less than 40 ps. The VGA is fabricated in a 90-nm CMOS process with a chip size (including all pads) of <inline-formula> <tex-math notation="LaTeX">$0.52\times0.5$ </tex-math></inline-formula> mm<sup>2</sup>. |
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| ISSN: | 2169-3536 |