Improved three-phase dynamic current mode logic-based D flip-flop design against power attacks(基于DyCML的改进型三阶段抗功耗攻击型D触发器)
Differential Power Attack (DPA) brings a significant security challenge for hardware, as it involves the examination of power consumption data from circuits to extract sensitive information. The security performance of a circuit is intrinsically linked to the resilience of its flip-flop components a...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
Zhejiang University Press
2025-07-01
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| Series: | Zhejiang Daxue xuebao. Lixue ban |
| Online Access: | https://doi.org/10.3785/j.issn.1008-9497.2025.04.002 |
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| Summary: | Differential Power Attack (DPA) brings a significant security challenge for hardware, as it involves the examination of power consumption data from circuits to extract sensitive information. The security performance of a circuit is intrinsically linked to the resilience of its flip-flop components against power attacks. This paper presents a novel design for a D flip-flop that is resistant to power consumption attacks, utilizing the DyCML structure. The proposed design incorporates a three-phase logic to avoid security vulnerabilities arising from unbalanced load capacitance within the circuit. Furthermore, the three-phase logic is enhanced by employing internal node signals to generate the discharge signal, thereby preventing potential attackers from compromising the discharge signal's integrity by manipulating the clock frequency, which could undermine the circuit's resistance to power consumption attacks. Through Hspice simulations, with two introduced parameters, i.e., normalized energy deviation (NED) and normalized standard deviation (NSD), the performance of the proposed TDyCML_FF is compared with several existing power attack-resistant flip-flop designs. The results indicate that the TDyCML_FF has better performance in terms of resistance to power attacks.功耗攻击是一种通过统计电路的功耗信息得到敏感数据信息的攻击手段。作为电路的重要组成单元，触发器的抗功耗攻击水平与电路的安全性能息息相关，为此提出一种抗功耗攻击型触发器。通过引入“预充电-求值-放电”三阶段逻辑，提出了改进型的三阶段动态电流模式逻辑D触发器（improved three-phase dynamic current mode logic-based D flip-flop，TDyCML_FF），避免了因负载电容不均衡引起的电路功耗不恒定等安全问题。同时对三阶段逻辑结构进行了改进，由电路内部节点信号生成放电信号，从而避免通过减缓时钟频率或消除放电信号对其进行攻击，提高了电路的抗功耗攻击性能。通过Hspice仿真实验，并引入归一化能量偏差（NED）和归一化标准偏差（NSD）2个量化参数，将TDyCML_FF感应放大逻辑触发器（SABL_FF）、三阶段双轨预充电逻辑触发器（TDPL_FF）等抗功耗攻击型触发器进行了对比，证明TDyCML_FF具有较高的抗功耗攻击性能。 |
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| ISSN: | 1008-9497 |