A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box
The “S-box” algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many re...
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| Format: | Article |
| Language: | English |
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Wiley
2013-01-01
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| Series: | Journal of Engineering |
| Online Access: | http://dx.doi.org/10.1155/2013/785126 |
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| author | Jia Hao Kong Li-Minn Ang Kah Phooi Seng |
| author_facet | Jia Hao Kong Li-Minn Ang Kah Phooi Seng |
| author_sort | Jia Hao Kong |
| collection | DOAJ |
| description | The “S-box” algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many researchers is to find a compact and small hardware footprint for the S-box circuit. In this paper, we present our version of minimized S-box with two separate proposals and improvements in the overall gate count. The compact S-box is adopted with a compact and optimum processor architecture specifically tailored for the AES, namely, the compact instruction set architecture (CISA). To further justify and strengthen the purpose of the compact crypto-processor’s application, we have also presented a selective encryption architecture (SEA) which incorporates the CISA as a part of the encryption core, accompanied by the set partitioning in hierarchical trees (SPIHT) algorithm as a complete selective encryption system. |
| format | Article |
| id | doaj-art-c7ceda9dbec14b85b2131f5d5eb8441a |
| institution | OA Journals |
| issn | 2314-4904 2314-4912 |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Engineering |
| spelling | doaj-art-c7ceda9dbec14b85b2131f5d5eb8441a2025-08-20T02:20:05ZengWileyJournal of Engineering2314-49042314-49122013-01-01201310.1155/2013/785126785126A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-BoxJia Hao Kong0Li-Minn Ang1Kah Phooi Seng2Department of Electrical and Electronic Engineering, University of Nottingham, Malaysia Campus, 43500 Semenyih, MalaysiaSchool of Engineering, Edith Cowan University, Joondalup, WA 6027, AustraliaSchool of Engineering, Edith Cowan University, Joondalup, WA 6027, AustraliaThe “S-box” algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many researchers is to find a compact and small hardware footprint for the S-box circuit. In this paper, we present our version of minimized S-box with two separate proposals and improvements in the overall gate count. The compact S-box is adopted with a compact and optimum processor architecture specifically tailored for the AES, namely, the compact instruction set architecture (CISA). To further justify and strengthen the purpose of the compact crypto-processor’s application, we have also presented a selective encryption architecture (SEA) which incorporates the CISA as a part of the encryption core, accompanied by the set partitioning in hierarchical trees (SPIHT) algorithm as a complete selective encryption system.http://dx.doi.org/10.1155/2013/785126 |
| spellingShingle | Jia Hao Kong Li-Minn Ang Kah Phooi Seng A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box Journal of Engineering |
| title | A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box |
| title_full | A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box |
| title_fullStr | A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box |
| title_full_unstemmed | A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box |
| title_short | A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box |
| title_sort | very compact aes spiht selective encryption computer architecture design with improved s box |
| url | http://dx.doi.org/10.1155/2013/785126 |
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