IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance
Intellectual property (IP) core based design is an emerging design methodology to deal with increasing chip design complexity. C/C++ based high level synthesis (HLS) is also gaining traction as a design methodology to deal with increasing design complexity. In the work presented here, we present a d...
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| Format: | Article |
| Language: | English |
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Wiley
2014-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2014/418750 |
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| author | Sharad Sinha Thambipillai Srikanthan |
| author_facet | Sharad Sinha Thambipillai Srikanthan |
| author_sort | Sharad Sinha |
| collection | DOAJ |
| description | Intellectual property (IP) core based design is an emerging design methodology to deal with increasing chip design complexity. C/C++ based high level synthesis (HLS) is also gaining traction as a design methodology to deal with increasing design complexity. In the work presented here, we present a design methodology that combines these two individual methodologies and is therefore more powerful. We discuss our proposed methodology in the context of supporting efficient hardware synthesis of a class of mathematical functions without altering original C/C++ source code. Additionally, we also discuss and propose methods to integrate legacy IP cores in existing HLS flows. Relying on concepts from the domains of program recognition and optimized low level implementations of such arithmetic functions, the described design methodology is a step towards intelligent synthesis where application characteristics are matched with specific architectural resources and relevant IP cores in a transparent manner for improved area-delay results. The combined methodology is more aware of the target hardware architecture than the conventional HLS flow. Implementation results of certain compute kernels from a commercial tool Vivado-HLS as well as proposed flow are also compared to show that proposed flow gives better results. |
| format | Article |
| id | doaj-art-c42d810e0ff64b52a84d5bccb21d4efa |
| institution | DOAJ |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2014-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-c42d810e0ff64b52a84d5bccb21d4efa2025-08-20T03:23:11ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092014-01-01201410.1155/2014/418750418750IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design PerformanceSharad Sinha0Thambipillai Srikanthan1CHiPES, School of Computer Engineering, Nanyang Technological University, Nanyang Avenue, 639798, SingaporeCHiPES, School of Computer Engineering, Nanyang Technological University, Nanyang Avenue, 639798, SingaporeIntellectual property (IP) core based design is an emerging design methodology to deal with increasing chip design complexity. C/C++ based high level synthesis (HLS) is also gaining traction as a design methodology to deal with increasing design complexity. In the work presented here, we present a design methodology that combines these two individual methodologies and is therefore more powerful. We discuss our proposed methodology in the context of supporting efficient hardware synthesis of a class of mathematical functions without altering original C/C++ source code. Additionally, we also discuss and propose methods to integrate legacy IP cores in existing HLS flows. Relying on concepts from the domains of program recognition and optimized low level implementations of such arithmetic functions, the described design methodology is a step towards intelligent synthesis where application characteristics are matched with specific architectural resources and relevant IP cores in a transparent manner for improved area-delay results. The combined methodology is more aware of the target hardware architecture than the conventional HLS flow. Implementation results of certain compute kernels from a commercial tool Vivado-HLS as well as proposed flow are also compared to show that proposed flow gives better results.http://dx.doi.org/10.1155/2014/418750 |
| spellingShingle | Sharad Sinha Thambipillai Srikanthan IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance International Journal of Reconfigurable Computing |
| title | IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance |
| title_full | IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance |
| title_fullStr | IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance |
| title_full_unstemmed | IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance |
| title_short | IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance |
| title_sort | ip enabled c c based high level synthesis a step towards better designer productivity and design performance |
| url | http://dx.doi.org/10.1155/2014/418750 |
| work_keys_str_mv | AT sharadsinha ipenabledccbasedhighlevelsynthesisasteptowardsbetterdesignerproductivityanddesignperformance AT thambipillaisrikanthan ipenabledccbasedhighlevelsynthesisasteptowardsbetterdesignerproductivityanddesignperformance |