A novel 8T SRAM cell using PFC and PPC VS-CNTFET transistor
Abstract The 8T static random-access memory (SRAM) cell using carbon nanotube technology, positive feedback, and dynamic supply voltage scaling are presented in this work. Positive feedback strengthens the feedback loop and enhances the noise margin making SRAM cells less susceptible to disturbance...
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SpringerOpen
2025-01-01
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| Series: | Journal of Engineering and Applied Science |
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| Online Access: | https://doi.org/10.1186/s44147-025-00579-y |
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| author | Vipin Kumar Sharma Abhishek Kumar |
| author_facet | Vipin Kumar Sharma Abhishek Kumar |
| author_sort | Vipin Kumar Sharma |
| collection | DOAJ |
| description | Abstract The 8T static random-access memory (SRAM) cell using carbon nanotube technology, positive feedback, and dynamic supply voltage scaling are presented in this work. Positive feedback strengthens the feedback loop and enhances the noise margin making SRAM cells less susceptible to disturbance and improving the stabilization of the cell by improving read and write timing response. Positive feedback control (PFC) adjusts the cell’s operating condition based on its current and external condition under varying conditions. The positive power supply controlled (PPC) technique in SRAM cell design improves the stability and leakage power consumption by adjusting the voltage level during the operation mode of the cell. The experiment with carbon nanotube field-effect transistor (CNTFET) offers higher drive current and lower power consumption compared to conventional silicon-based transistors. The performance of the 8T SRAM cell incorporating PFC and PPC transistor is investigated with Synopsys HSPICE using the Stanford CNFET model. The proposed SRAM cell architecture archives a 99.99% improvement in power consumption and delay product (PDP) compared to a conventional 6T SRAM cell. The static noise margin of 300 mV ensures better noise immunity and reliable retention of data. The mean value of power consumption is 43.19 nW showing a variance of 93.16 fW and a standard deviation (σ) of 305.2 nW and the mean value of delay is 14.71 ps showing a variance of 1.010 and a standard deviation (σ) of 10.05 ps. CNTFET 8T SRAM cell with the combination of positive feedback and dynamic feedback enhances the performance and efficiency of the memory cell under varying conditions. |
| format | Article |
| id | doaj-art-c325e8084f3347f0931c15e95bf7d36d |
| institution | Kabale University |
| issn | 1110-1903 2536-9512 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | SpringerOpen |
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| series | Journal of Engineering and Applied Science |
| spelling | doaj-art-c325e8084f3347f0931c15e95bf7d36d2025-01-19T12:25:20ZengSpringerOpenJournal of Engineering and Applied Science1110-19032536-95122025-01-0172112110.1186/s44147-025-00579-yA novel 8T SRAM cell using PFC and PPC VS-CNTFET transistorVipin Kumar Sharma0Abhishek Kumar1School of Electronics and Electrical Engineering, Lovely Professional UniversitySchool of Electronics and Electrical Engineering, Lovely Professional UniversityAbstract The 8T static random-access memory (SRAM) cell using carbon nanotube technology, positive feedback, and dynamic supply voltage scaling are presented in this work. Positive feedback strengthens the feedback loop and enhances the noise margin making SRAM cells less susceptible to disturbance and improving the stabilization of the cell by improving read and write timing response. Positive feedback control (PFC) adjusts the cell’s operating condition based on its current and external condition under varying conditions. The positive power supply controlled (PPC) technique in SRAM cell design improves the stability and leakage power consumption by adjusting the voltage level during the operation mode of the cell. The experiment with carbon nanotube field-effect transistor (CNTFET) offers higher drive current and lower power consumption compared to conventional silicon-based transistors. The performance of the 8T SRAM cell incorporating PFC and PPC transistor is investigated with Synopsys HSPICE using the Stanford CNFET model. The proposed SRAM cell architecture archives a 99.99% improvement in power consumption and delay product (PDP) compared to a conventional 6T SRAM cell. The static noise margin of 300 mV ensures better noise immunity and reliable retention of data. The mean value of power consumption is 43.19 nW showing a variance of 93.16 fW and a standard deviation (σ) of 305.2 nW and the mean value of delay is 14.71 ps showing a variance of 1.010 and a standard deviation (σ) of 10.05 ps. CNTFET 8T SRAM cell with the combination of positive feedback and dynamic feedback enhances the performance and efficiency of the memory cell under varying conditions.https://doi.org/10.1186/s44147-025-00579-ySRAM8T cellPPCPFCCNTFETLow power |
| spellingShingle | Vipin Kumar Sharma Abhishek Kumar A novel 8T SRAM cell using PFC and PPC VS-CNTFET transistor Journal of Engineering and Applied Science SRAM 8T cell PPC PFC CNTFET Low power |
| title | A novel 8T SRAM cell using PFC and PPC VS-CNTFET transistor |
| title_full | A novel 8T SRAM cell using PFC and PPC VS-CNTFET transistor |
| title_fullStr | A novel 8T SRAM cell using PFC and PPC VS-CNTFET transistor |
| title_full_unstemmed | A novel 8T SRAM cell using PFC and PPC VS-CNTFET transistor |
| title_short | A novel 8T SRAM cell using PFC and PPC VS-CNTFET transistor |
| title_sort | novel 8t sram cell using pfc and ppc vs cntfet transistor |
| topic | SRAM 8T cell PPC PFC CNTFET Low power |
| url | https://doi.org/10.1186/s44147-025-00579-y |
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