New Insight on the Application of Binary Coded Chiliad (BCC) Encoding for Decimal Arithmetic
The densely packed decimal (DPD) encoding for secondary and primary storage of three binary coded decimal (BCD) digits is included in the IEEE 754-2019 standard for decimal floating-point arithmetic. Binary coded chiliad (BCC) representation of 3 BCD digits (i.e. radix-1000) will achieve equi-effici...
Saved in:
| Main Author: | |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Amirkabir University of Technology
2021-06-01
|
| Series: | AUT Journal of Electrical Engineering |
| Subjects: | |
| Online Access: | https://eej.aut.ac.ir/article_4210_53a14fd5d4d3ccc80f25de0bb0c8f088.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1849431064142938112 |
|---|---|
| author | Morteza Dorrigiv |
| author_facet | Morteza Dorrigiv |
| author_sort | Morteza Dorrigiv |
| collection | DOAJ |
| description | The densely packed decimal (DPD) encoding for secondary and primary storage of three binary coded decimal (BCD) digits is included in the IEEE 754-2019 standard for decimal floating-point arithmetic. Binary coded chiliad (BCC) representation of 3 BCD digits (i.e. radix-1000) will achieve equi-efficient packing. The primary advantage is BCC operands can be directly manipulated by arithmetic operations, while DPD operands have to undergo DPD-to-BCD and reverse conversions afore and ahead of each arithmetic operation. Therefore, we are interested in designing the arithmetic unit that receives BCC operands and produces BCC results, following previous BCC works. Compared to the equivalent BCD or other radix-10 arithmetic, prospects show that equally efficient arithmetic units are feasible for BCC arithmetic, as even better performance has been achieved in the case of addition. Therefore, we demonstrate the IEEE 754-2019 compatibility of the BCC Encoding in this paper. Consequently, for the DPD-to-BCD expansion and the reverse compression, the DPD-to-BCC converter, and the reverse blocks, we show the delay, area, and power dissipation. The findings show a substantial delay (83%), area (27%), and power (29%) overhead. However, as the number of conversions in the latter case is much less than the former, overall power dissipation is expected to decrease considerably. |
| format | Article |
| id | doaj-art-c30f69ca5ad54b19af8b2bdb18c46991 |
| institution | Kabale University |
| issn | 2588-2910 2588-2929 |
| language | English |
| publishDate | 2021-06-01 |
| publisher | Amirkabir University of Technology |
| record_format | Article |
| series | AUT Journal of Electrical Engineering |
| spelling | doaj-art-c30f69ca5ad54b19af8b2bdb18c469912025-08-20T03:27:44ZengAmirkabir University of TechnologyAUT Journal of Electrical Engineering2588-29102588-29292021-06-01531475610.22060/eej.2020.19022.53794210New Insight on the Application of Binary Coded Chiliad (BCC) Encoding for Decimal ArithmeticMorteza Dorrigiv0Electrical and Computer Engineering Dept., Semnan University, Semnan, Iran.The densely packed decimal (DPD) encoding for secondary and primary storage of three binary coded decimal (BCD) digits is included in the IEEE 754-2019 standard for decimal floating-point arithmetic. Binary coded chiliad (BCC) representation of 3 BCD digits (i.e. radix-1000) will achieve equi-efficient packing. The primary advantage is BCC operands can be directly manipulated by arithmetic operations, while DPD operands have to undergo DPD-to-BCD and reverse conversions afore and ahead of each arithmetic operation. Therefore, we are interested in designing the arithmetic unit that receives BCC operands and produces BCC results, following previous BCC works. Compared to the equivalent BCD or other radix-10 arithmetic, prospects show that equally efficient arithmetic units are feasible for BCC arithmetic, as even better performance has been achieved in the case of addition. Therefore, we demonstrate the IEEE 754-2019 compatibility of the BCC Encoding in this paper. Consequently, for the DPD-to-BCD expansion and the reverse compression, the DPD-to-BCC converter, and the reverse blocks, we show the delay, area, and power dissipation. The findings show a substantial delay (83%), area (27%), and power (29%) overhead. However, as the number of conversions in the latter case is much less than the former, overall power dissipation is expected to decrease considerably.https://eej.aut.ac.ir/article_4210_53a14fd5d4d3ccc80f25de0bb0c8f088.pdfbinary coded chiliad encodingdecimal computer arithmeticieee 754-2019densely packed decimal encodingencoding conversion |
| spellingShingle | Morteza Dorrigiv New Insight on the Application of Binary Coded Chiliad (BCC) Encoding for Decimal Arithmetic AUT Journal of Electrical Engineering binary coded chiliad encoding decimal computer arithmetic ieee 754-2019 densely packed decimal encoding encoding conversion |
| title | New Insight on the Application of Binary Coded Chiliad (BCC) Encoding for Decimal Arithmetic |
| title_full | New Insight on the Application of Binary Coded Chiliad (BCC) Encoding for Decimal Arithmetic |
| title_fullStr | New Insight on the Application of Binary Coded Chiliad (BCC) Encoding for Decimal Arithmetic |
| title_full_unstemmed | New Insight on the Application of Binary Coded Chiliad (BCC) Encoding for Decimal Arithmetic |
| title_short | New Insight on the Application of Binary Coded Chiliad (BCC) Encoding for Decimal Arithmetic |
| title_sort | new insight on the application of binary coded chiliad bcc encoding for decimal arithmetic |
| topic | binary coded chiliad encoding decimal computer arithmetic ieee 754-2019 densely packed decimal encoding encoding conversion |
| url | https://eej.aut.ac.ir/article_4210_53a14fd5d4d3ccc80f25de0bb0c8f088.pdf |
| work_keys_str_mv | AT mortezadorrigiv newinsightontheapplicationofbinarycodedchiliadbccencodingfordecimalarithmetic |