Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs
Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to support high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in place to generate the desired frequency and to drive the...
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| Format: | Article |
| Language: | English |
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Wiley
2011-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2011/671546 |
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| _version_ | 1849685121690501120 |
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| author | Christian Schuck Bastian Haetzer Jürgen Becker |
| author_facet | Christian Schuck Bastian Haetzer Jürgen Becker |
| author_sort | Christian Schuck |
| collection | DOAJ |
| description | Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to support high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in place to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all designs run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of partial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to dynamically self-adopt the clock frequency during runtime by reconfiguring the Digital Clock Managers. We also present a method for online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be used as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further, the tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the distributed dynamic frequency scaling method with little additional overhead. |
| format | Article |
| id | doaj-art-c2c26909d93249d0b75a295bc32b9e96 |
| institution | DOAJ |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2011-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-c2c26909d93249d0b75a295bc32b9e962025-08-20T03:23:15ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092011-01-01201110.1155/2011/671546671546Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAsChristian Schuck0Bastian Haetzer1Jürgen Becker2Institut für Technik der Informationsverarbeitung (ITIV), Karlsruher Institut für Technologie (KIT), Vincenz-Prießnitz-Straße 1, 76131 Karlsruhe, GermanyInstitut für Technik der Informationsverarbeitung (ITIV), Karlsruher Institut für Technologie (KIT), Vincenz-Prießnitz-Straße 1, 76131 Karlsruhe, GermanyInstitut für Technik der Informationsverarbeitung (ITIV), Karlsruher Institut für Technologie (KIT), Vincenz-Prießnitz-Straße 1, 76131 Karlsruhe, GermanyXilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to support high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in place to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all designs run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of partial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to dynamically self-adopt the clock frequency during runtime by reconfiguring the Digital Clock Managers. We also present a method for online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be used as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further, the tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the distributed dynamic frequency scaling method with little additional overhead.http://dx.doi.org/10.1155/2011/671546 |
| spellingShingle | Christian Schuck Bastian Haetzer Jürgen Becker Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs International Journal of Reconfigurable Computing |
| title | Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs |
| title_full | Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs |
| title_fullStr | Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs |
| title_full_unstemmed | Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs |
| title_short | Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs |
| title_sort | reconfiguration techniques for self x power and performance management on xilinx virtex ii virtex ii pro fpgas |
| url | http://dx.doi.org/10.1155/2011/671546 |
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