A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback
Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources, power, and performance. Yet, progress in dynamically reconfigurable computing is fundamentally limited by the reconfiguration time overhead. Prior research in the development of dyn...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2011-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2011/439072 |
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| Summary: | Dynamically reconfigurable computing platforms provide promising
methods for dynamic management of hardware resources, power, and
performance. Yet, progress in dynamically reconfigurable computing
is fundamentally limited by the reconfiguration time overhead.
Prior research in the development of dynamic partial
reconfiguration (DPR) controllers has been limited by its use of
the Processor Local Bus (PLB). As a result, the bus was
unavailable during DPR. This resulted in significant time
overhead. To minimize the overhead, we introduce the use of a
multiport memory controller (MPMC) that frees the PLB during the
reconfiguration process. The processor is thus allowed to switch
to other tasks during the reconfiguration operation. This
effectively limits the reconfiguration overhead. An interrupt is
used to inform the processor when the operation is complete.
Therefore, the system can multitask during the reconfiguration
operation. Furthermore, to maximize performance, we introduce the
use of overclocking with active feedback. During overclocking, the
use of active feedback is used to ensure that the device voltage
and temperature are within nominal operating conditions. All of
these contributions lead to significant performance improvements
over current partial reconfiguration subsystems. The portability
of the system, demonstrated on the Virtex-4 and the Virtex-5,
consists of four different hardware platforms. |
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| ISSN: | 1687-7195 1687-7209 |