A 35 nV/√Hz Analog Front-End Circuit with Adjustable Bandwidth and Gain in UMC 40 nm CMOS for Biopotential Signal Acquisition

This paper presents a 35 nV/√Hz analog front-end (AFE) circuitdesigned in the UMC 40 nm CMOS technology for the acquisition of biopotential signal. The proposed AFE consists of a capacitive-coupled instrumentation amplifier (CCIA) and a combination of a programmable gain amplifier (PGA) and a low-pa...

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Main Authors: Lu Liu, Bin Wang, Yiren Xu, Xiaokun Lin, Weitao Yang, Yinglong Ding
Format: Article
Language:English
Published: MDPI AG 2024-12-01
Series:Sensors
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Online Access:https://www.mdpi.com/1424-8220/24/24/7994
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author Lu Liu
Bin Wang
Yiren Xu
Xiaokun Lin
Weitao Yang
Yinglong Ding
author_facet Lu Liu
Bin Wang
Yiren Xu
Xiaokun Lin
Weitao Yang
Yinglong Ding
author_sort Lu Liu
collection DOAJ
description This paper presents a 35 nV/√Hz analog front-end (AFE) circuitdesigned in the UMC 40 nm CMOS technology for the acquisition of biopotential signal. The proposed AFE consists of a capacitive-coupled instrumentation amplifier (CCIA) and a combination of a programmable gain amplifier (PGA) and a low-pass filter (LPF). The CCIA includes a DC servo loop (DSL) to eliminate electrode DC offset (EDO) and a ripple rejection loop (RRL) with self-zeroing technology to suppress high-frequency ripples caused by the chopper. The PGA-LPF is realized using switched-capacitor circuits, enabling adjustable gain and bandwidth. Implemented in theUMC 40 nm CMOS process, the AFE achieves an input impedance of 368 MΩ at 50 Hz, a common-mode rejection ratio (CMRR) of 111 dB, an equivalent input noise of 1.04 μVrms over the 0.5–1 kHz range, and a maximum elimination of 50 mV electrode DC offset voltage. It occupies an area of only 0.39 × 0.47 mm<sup>2</sup> on the chip, with a power consumption of 8.96 μW.
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issn 1424-8220
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spelling doaj-art-bec15089dd8f4d75bcf84bf7a274172d2025-08-20T02:43:21ZengMDPI AGSensors1424-82202024-12-012424799410.3390/s24247994A 35 nV/√Hz Analog Front-End Circuit with Adjustable Bandwidth and Gain in UMC 40 nm CMOS for Biopotential Signal AcquisitionLu Liu0Bin Wang1Yiren Xu2Xiaokun Lin3Weitao Yang4Yinglong Ding5State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaState Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaState Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaState Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaState Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaState Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaThis paper presents a 35 nV/√Hz analog front-end (AFE) circuitdesigned in the UMC 40 nm CMOS technology for the acquisition of biopotential signal. The proposed AFE consists of a capacitive-coupled instrumentation amplifier (CCIA) and a combination of a programmable gain amplifier (PGA) and a low-pass filter (LPF). The CCIA includes a DC servo loop (DSL) to eliminate electrode DC offset (EDO) and a ripple rejection loop (RRL) with self-zeroing technology to suppress high-frequency ripples caused by the chopper. The PGA-LPF is realized using switched-capacitor circuits, enabling adjustable gain and bandwidth. Implemented in theUMC 40 nm CMOS process, the AFE achieves an input impedance of 368 MΩ at 50 Hz, a common-mode rejection ratio (CMRR) of 111 dB, an equivalent input noise of 1.04 μVrms over the 0.5–1 kHz range, and a maximum elimination of 50 mV electrode DC offset voltage. It occupies an area of only 0.39 × 0.47 mm<sup>2</sup> on the chip, with a power consumption of 8.96 μW.https://www.mdpi.com/1424-8220/24/24/7994capacitively-coupled chopper instrumentation amplifierlow noisedc servo loopripple reduction loopbandwidth-gain adjustablebiopotential signal acquisition
spellingShingle Lu Liu
Bin Wang
Yiren Xu
Xiaokun Lin
Weitao Yang
Yinglong Ding
A 35 nV/√Hz Analog Front-End Circuit with Adjustable Bandwidth and Gain in UMC 40 nm CMOS for Biopotential Signal Acquisition
Sensors
capacitively-coupled chopper instrumentation amplifier
low noise
dc servo loop
ripple reduction loop
bandwidth-gain adjustable
biopotential signal acquisition
title A 35 nV/√Hz Analog Front-End Circuit with Adjustable Bandwidth and Gain in UMC 40 nm CMOS for Biopotential Signal Acquisition
title_full A 35 nV/√Hz Analog Front-End Circuit with Adjustable Bandwidth and Gain in UMC 40 nm CMOS for Biopotential Signal Acquisition
title_fullStr A 35 nV/√Hz Analog Front-End Circuit with Adjustable Bandwidth and Gain in UMC 40 nm CMOS for Biopotential Signal Acquisition
title_full_unstemmed A 35 nV/√Hz Analog Front-End Circuit with Adjustable Bandwidth and Gain in UMC 40 nm CMOS for Biopotential Signal Acquisition
title_short A 35 nV/√Hz Analog Front-End Circuit with Adjustable Bandwidth and Gain in UMC 40 nm CMOS for Biopotential Signal Acquisition
title_sort 35 nv √hz analog front end circuit with adjustable bandwidth and gain in umc 40 nm cmos for biopotential signal acquisition
topic capacitively-coupled chopper instrumentation amplifier
low noise
dc servo loop
ripple reduction loop
bandwidth-gain adjustable
biopotential signal acquisition
url https://www.mdpi.com/1424-8220/24/24/7994
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