A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation

A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation

This article presents a fully synthesizable digital PLL supported by a feedforward phase noise cancellation (FPNC) path. With the FPNC path, the rms jitter of the DPLL was enhanced (reduced) by around 25% at different output frequencies. A gain mismatch calibration circuit was proposed to maintain t...

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Bibliographic Details
Main Authors: Waleed Madany, Yuncheng Zhang, Ashbir Aviat Fadila, Hongye Huang, Junjun Qiu, Jill Mayeda, Atsushi Shirane, Kenichi Okada
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
FPNC
DPLL
synthesizable
TDC
DCDL
DLL
Online Access:https://ieeexplore.ieee.org/document/10909072/
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