A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation
This article presents a fully synthesizable digital PLL supported by a feedforward phase noise cancellation (FPNC) path. With the FPNC path, the rms jitter of the DPLL was enhanced (reduced) by around 25% at different output frequencies. A gain mismatch calibration circuit was proposed to maintain t...
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| Format: | Article |
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10909072/ |
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| author | Waleed Madany Yuncheng Zhang Ashbir Aviat Fadila Hongye Huang Junjun Qiu Jill Mayeda Atsushi Shirane Kenichi Okada |
| author_facet | Waleed Madany Yuncheng Zhang Ashbir Aviat Fadila Hongye Huang Junjun Qiu Jill Mayeda Atsushi Shirane Kenichi Okada |
| author_sort | Waleed Madany |
| collection | DOAJ |
| description | This article presents a fully synthesizable digital PLL supported by a feedforward phase noise cancellation (FPNC) path. With the FPNC path, the rms jitter of the DPLL was enhanced (reduced) by around 25% at different output frequencies. A gain mismatch calibration circuit was proposed to maintain this jitter enhancement over different process, voltage, and temperature (PVT) variations. A proof-of-concept chip was built in 65 nm CMOS technology with an area of 0.105 mm2. At an output frequency of 1.0 GHz, the rms jitter of the DPLL was decreased from 1.0 ps to 753 fs with the cost of around 0.7 mW power consumption due to the FPNC path and the calibration circuit. This jitter reduction improves FoM from -234.4 to -236.0 dB. To confirm the effectiveness of the FPNC path and its background calibration circuit, different measurements were performed under different output frequencies, supply voltages, bandwidths, and chips, revealing a performance enhancement under all those conditions. |
| format | Article |
| id | doaj-art-bcb5e2839eab4929bd3abc6f08cc65fd |
| institution | DOAJ |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-bcb5e2839eab4929bd3abc6f08cc65fd2025-08-20T02:58:18ZengIEEEIEEE Access2169-35362025-01-0113402104022510.1109/ACCESS.2025.354736610909072A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise CancellationWaleed Madany0https://orcid.org/0000-0002-5653-9983Yuncheng Zhang1https://orcid.org/0000-0001-6467-3667Ashbir Aviat Fadila2https://orcid.org/0000-0002-5529-8217Hongye Huang3https://orcid.org/0000-0001-6071-2075Junjun Qiu4https://orcid.org/0000-0002-3698-4369Jill Mayeda5https://orcid.org/0000-0002-0575-291XAtsushi Shirane6Kenichi Okada7https://orcid.org/0000-0002-1082-7672Department of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, JapanDepartment of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, JapanDepartment of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, JapanDepartment of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, JapanDepartment of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, JapanDepartment of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, JapanDepartment of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, JapanDepartment of Electrical and Electronic Engineering, Institute of Science Tokyo, Tokyo, JapanThis article presents a fully synthesizable digital PLL supported by a feedforward phase noise cancellation (FPNC) path. With the FPNC path, the rms jitter of the DPLL was enhanced (reduced) by around 25% at different output frequencies. A gain mismatch calibration circuit was proposed to maintain this jitter enhancement over different process, voltage, and temperature (PVT) variations. A proof-of-concept chip was built in 65 nm CMOS technology with an area of 0.105 mm2. At an output frequency of 1.0 GHz, the rms jitter of the DPLL was decreased from 1.0 ps to 753 fs with the cost of around 0.7 mW power consumption due to the FPNC path and the calibration circuit. This jitter reduction improves FoM from -234.4 to -236.0 dB. To confirm the effectiveness of the FPNC path and its background calibration circuit, different measurements were performed under different output frequencies, supply voltages, bandwidths, and chips, revealing a performance enhancement under all those conditions.https://ieeexplore.ieee.org/document/10909072/FPNCDPLLsynthesizableTDCDCDLDLL |
| spellingShingle | Waleed Madany Yuncheng Zhang Ashbir Aviat Fadila Hongye Huang Junjun Qiu Jill Mayeda Atsushi Shirane Kenichi Okada A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation IEEE Access FPNC DPLL synthesizable TDC DCDL DLL |
| title | A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation |
| title_full | A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation |
| title_fullStr | A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation |
| title_full_unstemmed | A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation |
| title_short | A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation |
| title_sort | 0 8 x2013 1 4 ghz synthesizable dpll using a background gain mismatch calibrated feedforward phase noise cancellation |
| topic | FPNC DPLL synthesizable TDC DCDL DLL |
| url | https://ieeexplore.ieee.org/document/10909072/ |
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