Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow R<sub>ON,sp</sub>
An integrated quasi-vertical double-diffused MOSFET (DMOS) with split-gate trench (SGT) structure (SGT-QVDMOS), whose specific ON-state resistance (R<sub>ON,sp</sub>) breaks the traditional Si limit significantly, is proposed and fabricated. The measured data of the latest manufactured d...
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MDPI AG
2025-01-01
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| author | Feng Lin Tuanzhuang Wu Weidong Wang Zhengxuan Wang Yi Zhang Sheng Li Ran Ye Long Zhang Jiaxing Wei Siyang Liu Weifeng Sun |
| author_facet | Feng Lin Tuanzhuang Wu Weidong Wang Zhengxuan Wang Yi Zhang Sheng Li Ran Ye Long Zhang Jiaxing Wei Siyang Liu Weifeng Sun |
| author_sort | Feng Lin |
| collection | DOAJ |
| description | An integrated quasi-vertical double-diffused MOSFET (DMOS) with split-gate trench (SGT) structure (SGT-QVDMOS), whose specific ON-state resistance (R<sub>ON,sp</sub>) breaks the traditional Si limit significantly, is proposed and fabricated. The measured data of the latest manufactured device is presented. By introducing the vertical gate poly, the split grounded source poly, and the asymmetric thick oxide in the gate trench, the traditional lateral drift region is folded in the SGT-QVDMOS. In this way, the device voltage withstanding mode transforms from one dimension to two dimensions, including the horizontal and the vertical directions. Combining the electric field modulation effect and the reduced lateral area, which benefit from the quasi-vertical structure, the forward conducting characteristic of the SGT-QVDMOS is effectively improved. According to the measured results from the SGT-QVDMOS manufactured by the 180 nm Bipolar-CMOS-DMOS (BCD) process, the ultralow ON-state resistance is obtained. The device achieves 1.9 V V<sub>TH</sub>, 11.07 mΩ∙mm<sup>2</sup> R<sub>ON,sp</sub>, and 48.6 V BV, which is 39.0% lower than the traditional Si limit. |
| format | Article |
| id | doaj-art-bbbce4a4c74044838145fa22624d886a |
| institution | DOAJ |
| issn | 2079-4991 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Nanomaterials |
| spelling | doaj-art-bbbce4a4c74044838145fa22624d886a2025-08-20T02:48:10ZengMDPI AGNanomaterials2079-49912025-01-0115317210.3390/nano15030172Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow R<sub>ON,sp</sub>Feng Lin0Tuanzhuang Wu1Weidong Wang2Zhengxuan Wang3Yi Zhang4Sheng Li5Ran Ye6Long Zhang7Jiaxing Wei8Siyang Liu9Weifeng Sun10National ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing 210096, ChinaNational ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing 210096, ChinaNational ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing 210096, ChinaNational ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing 210096, ChinaCSMC Technologies Corporation, Wuxi 214000, ChinaNational ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing 210096, ChinaNational ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing 210096, ChinaNational ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing 210096, ChinaNational ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing 210096, ChinaNational ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing 210096, ChinaNational ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing 210096, ChinaAn integrated quasi-vertical double-diffused MOSFET (DMOS) with split-gate trench (SGT) structure (SGT-QVDMOS), whose specific ON-state resistance (R<sub>ON,sp</sub>) breaks the traditional Si limit significantly, is proposed and fabricated. The measured data of the latest manufactured device is presented. By introducing the vertical gate poly, the split grounded source poly, and the asymmetric thick oxide in the gate trench, the traditional lateral drift region is folded in the SGT-QVDMOS. In this way, the device voltage withstanding mode transforms from one dimension to two dimensions, including the horizontal and the vertical directions. Combining the electric field modulation effect and the reduced lateral area, which benefit from the quasi-vertical structure, the forward conducting characteristic of the SGT-QVDMOS is effectively improved. According to the measured results from the SGT-QVDMOS manufactured by the 180 nm Bipolar-CMOS-DMOS (BCD) process, the ultralow ON-state resistance is obtained. The device achieves 1.9 V V<sub>TH</sub>, 11.07 mΩ∙mm<sup>2</sup> R<sub>ON,sp</sub>, and 48.6 V BV, which is 39.0% lower than the traditional Si limit.https://www.mdpi.com/2079-4991/15/3/172quasi-vertical structureDMOSSGTBCD processspecific ON-state resistance |
| spellingShingle | Feng Lin Tuanzhuang Wu Weidong Wang Zhengxuan Wang Yi Zhang Sheng Li Ran Ye Long Zhang Jiaxing Wei Siyang Liu Weifeng Sun Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow R<sub>ON,sp</sub> Nanomaterials quasi-vertical structure DMOS SGT BCD process specific ON-state resistance |
| title | Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow R<sub>ON,sp</sub> |
| title_full | Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow R<sub>ON,sp</sub> |
| title_fullStr | Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow R<sub>ON,sp</sub> |
| title_full_unstemmed | Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow R<sub>ON,sp</sub> |
| title_short | Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow R<sub>ON,sp</sub> |
| title_sort | demonstration of integrated quasi vertical dmos compatible with the bipolar cmos dmos process achieving ultralow r sub on sp sub |
| topic | quasi-vertical structure DMOS SGT BCD process specific ON-state resistance |
| url | https://www.mdpi.com/2079-4991/15/3/172 |
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