Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
Abstract The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short‐period orbits as well as increasing the randomness of the generated bit sequences,...
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Main Authors: | Mangal D. Gupta, Rajeev K. Chauhan |
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Format: | Article |
Language: | English |
Published: |
Wiley
2021-09-01
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Series: | IET Computers & Digital Techniques |
Subjects: | |
Online Access: | https://doi.org/10.1049/cdt2.12027 |
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