Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
Abstract The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short‐period orbits as well as increasing the randomness of the generated bit sequences,...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-09-01
|
| Series: | IET Computers & Digital Techniques |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cdt2.12027 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832546692468047872 |
|---|---|
| author | Mangal D. Gupta Rajeev K. Chauhan |
| author_facet | Mangal D. Gupta Rajeev K. Chauhan |
| author_sort | Mangal D. Gupta |
| collection | DOAJ |
| description | Abstract The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short‐period orbits as well as increasing the randomness of the generated bit sequences, the proposed algorithm periodically changes the seed parameters of the LCG blocks. The proposed clock divider‐based pseudorandom bit generator is compared with other LCG‐based realisations, showing great improvement. First, a clock divider is utilised for generating a maximum length of 22n pseudorandom bits for n‐bit operands size which leads to lowering the hardware cost. Secondly, it generates high‐speed random bits at a uniform clock rate with one initial clock latency. Third, the proposed technique provides good statistical properties. The proposed architecture is implemented using Verilog HDL and further prototyped on commercially available field programmable gate array (FPGA) devices Virtex‐5, Virtex‐7, and Artix‐7. The realisation of the proposed architecture in these FPGA devices accomplishes an improved data throughput and utilises minimum FPGA resources (in terms of look‐up‐tables and flip‐flops) which are compared with the existing techniques. The generated bit sequence from the experiment is further analysed briefly for sequence size and verified for randomness by using the National Institute of Standards and Technology benchmark test. |
| format | Article |
| id | doaj-art-ba4507240bf94340bb63b8e5c0a42b7d |
| institution | Kabale University |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-09-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-ba4507240bf94340bb63b8e5c0a42b7d2025-02-03T06:47:36ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-09-0115534936110.1049/cdt2.12027Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGAMangal D. Gupta0Rajeev K. Chauhan1Department of Electronics and Communication Engineering MMMUT Gorakhpur Uttar Pradesh IndiaDepartment of Electronics and Communication Engineering MMMUT Gorakhpur Uttar Pradesh IndiaAbstract The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short‐period orbits as well as increasing the randomness of the generated bit sequences, the proposed algorithm periodically changes the seed parameters of the LCG blocks. The proposed clock divider‐based pseudorandom bit generator is compared with other LCG‐based realisations, showing great improvement. First, a clock divider is utilised for generating a maximum length of 22n pseudorandom bits for n‐bit operands size which leads to lowering the hardware cost. Secondly, it generates high‐speed random bits at a uniform clock rate with one initial clock latency. Third, the proposed technique provides good statistical properties. The proposed architecture is implemented using Verilog HDL and further prototyped on commercially available field programmable gate array (FPGA) devices Virtex‐5, Virtex‐7, and Artix‐7. The realisation of the proposed architecture in these FPGA devices accomplishes an improved data throughput and utilises minimum FPGA resources (in terms of look‐up‐tables and flip‐flops) which are compared with the existing techniques. The generated bit sequence from the experiment is further analysed briefly for sequence size and verified for randomness by using the National Institute of Standards and Technology benchmark test.https://doi.org/10.1049/cdt2.12027clocksfield programmable gate arrayshardware description languagesrandom number generationrandom sequences |
| spellingShingle | Mangal D. Gupta Rajeev K. Chauhan Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA IET Computers & Digital Techniques clocks field programmable gate arrays hardware description languages random number generation random sequences |
| title | Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA |
| title_full | Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA |
| title_fullStr | Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA |
| title_full_unstemmed | Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA |
| title_short | Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA |
| title_sort | coupled variable input lcg and clock divider based large period pseudo random bit generator on fpga |
| topic | clocks field programmable gate arrays hardware description languages random number generation random sequences |
| url | https://doi.org/10.1049/cdt2.12027 |
| work_keys_str_mv | AT mangaldgupta coupledvariableinputlcgandclockdividerbasedlargeperiodpseudorandombitgeneratoronfpga AT rajeevkchauhan coupledvariableinputlcgandclockdividerbasedlargeperiodpseudorandombitgeneratoronfpga |