APA (7th ed.) Citation

Gupta, M. D., & Chauhan, R. K. Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA. Wiley.

Chicago Style (17th ed.) Citation

Gupta, Mangal D., and Rajeev K. Chauhan. Coupled Variable‐input LCG and Clock Divider‐based Large Period Pseudo‐random Bit Generator on FPGA. Wiley.

MLA (9th ed.) Citation

Gupta, Mangal D., and Rajeev K. Chauhan. Coupled Variable‐input LCG and Clock Divider‐based Large Period Pseudo‐random Bit Generator on FPGA. Wiley.