An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications
This paper presents an FPGA tech-mapping algorithm dedicated to security applications. The objective is to implement—on a full-custom asynchronous FPGA—secured functions that need to be robust against side-channel attacks (SCAs). The paper briefly describes the architecture of this FPGA that has bee...
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| Format: | Article |
| Language: | English |
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Wiley
2013-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2013/517947 |
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| _version_ | 1849686245305745408 |
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| author | Taha Beyrouthy Laurent Fesquet |
| author_facet | Taha Beyrouthy Laurent Fesquet |
| author_sort | Taha Beyrouthy |
| collection | DOAJ |
| description | This paper presents an FPGA tech-mapping algorithm dedicated to security applications. The objective is to implement—on a full-custom asynchronous FPGA—secured functions that need to be robust against side-channel attacks (SCAs). The paper briefly describes the architecture of this FPGA that has been designed and prototyped in CMOS 65 nm to target various styles of asynchronous logic including 2-phase and 4-phase communication protocols and 1-of-n data encoding. This programmable architecture is designed to be electrically balanced in order to fit the security requirements. It allows fair comparisons between different styles of asynchronous implementations. In order to illustrate the FPGA flexibility and security, a case study has been implemented in 2-phase and 4-phase Quasi-Delay-Insensitive (QDI) logic. |
| format | Article |
| id | doaj-art-b7cdbf78e04b43cf9e25fe04c28389a5 |
| institution | DOAJ |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-b7cdbf78e04b43cf9e25fe04c28389a52025-08-20T03:22:45ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092013-01-01201310.1155/2013/517947517947An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security ApplicationsTaha Beyrouthy0Laurent Fesquet1Laboratoire TIMA, 46 Avenue Félix Viallet, 38031 Grenoble, FranceLaboratoire TIMA, 46 Avenue Félix Viallet, 38031 Grenoble, FranceThis paper presents an FPGA tech-mapping algorithm dedicated to security applications. The objective is to implement—on a full-custom asynchronous FPGA—secured functions that need to be robust against side-channel attacks (SCAs). The paper briefly describes the architecture of this FPGA that has been designed and prototyped in CMOS 65 nm to target various styles of asynchronous logic including 2-phase and 4-phase communication protocols and 1-of-n data encoding. This programmable architecture is designed to be electrically balanced in order to fit the security requirements. It allows fair comparisons between different styles of asynchronous implementations. In order to illustrate the FPGA flexibility and security, a case study has been implemented in 2-phase and 4-phase Quasi-Delay-Insensitive (QDI) logic.http://dx.doi.org/10.1155/2013/517947 |
| spellingShingle | Taha Beyrouthy Laurent Fesquet An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications International Journal of Reconfigurable Computing |
| title | An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications |
| title_full | An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications |
| title_fullStr | An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications |
| title_full_unstemmed | An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications |
| title_short | An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications |
| title_sort | asynchronous fpga block with its tech mapping algorithm dedicated to security applications |
| url | http://dx.doi.org/10.1155/2013/517947 |
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