FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs
Recently, convolutional neural networks (CNNs) have received a massive amount of interest due to their ability to achieve high accuracy in various artificial intelligence tasks. With the development of complex CNN models, a significant drawback is their high computational burden and memory requireme...
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MDPI AG
2025-01-01
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| Series: | Applied Sciences |
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| author | Mustafa Tasci Ayhan Istanbullu Vedat Tumen Selahattin Kosunalp |
| author_facet | Mustafa Tasci Ayhan Istanbullu Vedat Tumen Selahattin Kosunalp |
| author_sort | Mustafa Tasci |
| collection | DOAJ |
| description | Recently, convolutional neural networks (CNNs) have received a massive amount of interest due to their ability to achieve high accuracy in various artificial intelligence tasks. With the development of complex CNN models, a significant drawback is their high computational burden and memory requirements. The performance of a typical CNN model can be enhanced by the improvement of hardware accelerators. Practical implementations on field-programmable gate arrays (FPGA) have the potential to reduce resource utilization while maintaining low power consumption. Nevertheless, when implementing complex CNN models on FPGAs, these may may require further computational and memory capacities, exceeding the available capacity provided by many current FPGAs. An effective solution to this issue is to use quantized neural network (QNN) models to remove the burden of full-precision weights and activations. This article proposes an accelerator design framework for FPGAs, called FPGA-QNN, with a particular value in reducing high computational burden and memory requirements when implementing CNNs. To approach this goal, FPGA-QNN exploits the basics of quantized neural network (QNN) models by converting the high burden of full-precision weights and activations into integer operations. The FPGA-QNN framework comes up with 12 accelerators based on multi-layer perceptron (MLP) and LeNet CNN models, each of which is associated with a specific combination of quantization and folding. The outputs from the performance evaluations on Xilinx PYNQ Z1 development board proved the superiority of FPGA-QNN in terms of resource utilization and energy efficiency in comparison to several recent approaches. The proposed MLP model classified the FashionMNIST dataset at a speed of 953 kFPS with 1019 GOPs while consuming 2.05 W. |
| format | Article |
| id | doaj-art-b524110d1cbf4a349f667b017f797c80 |
| institution | Kabale University |
| issn | 2076-3417 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | MDPI AG |
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| series | Applied Sciences |
| spelling | doaj-art-b524110d1cbf4a349f667b017f797c802025-01-24T13:20:28ZengMDPI AGApplied Sciences2076-34172025-01-0115268810.3390/app15020688FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAsMustafa Tasci0Ayhan Istanbullu1Vedat Tumen2Selahattin Kosunalp3Department of Computer Technologies, Gönen Vocational School, Bandırma Onyedi Eylül University, Bandırma 10200, TürkiyeDepartment of Computer Engineering, Faculty of Engineering, Balıkesir University, Balıkesir 10145, TürkiyeDepartment of Computer Engineering, Faculty of Engineering and Architecture, Bitlis Eren University, Bitlis 13100, TürkiyeDepartment of Computer Technologies, Gönen Vocational School, Bandırma Onyedi Eylül University, Bandırma 10200, TürkiyeRecently, convolutional neural networks (CNNs) have received a massive amount of interest due to their ability to achieve high accuracy in various artificial intelligence tasks. With the development of complex CNN models, a significant drawback is their high computational burden and memory requirements. The performance of a typical CNN model can be enhanced by the improvement of hardware accelerators. Practical implementations on field-programmable gate arrays (FPGA) have the potential to reduce resource utilization while maintaining low power consumption. Nevertheless, when implementing complex CNN models on FPGAs, these may may require further computational and memory capacities, exceeding the available capacity provided by many current FPGAs. An effective solution to this issue is to use quantized neural network (QNN) models to remove the burden of full-precision weights and activations. This article proposes an accelerator design framework for FPGAs, called FPGA-QNN, with a particular value in reducing high computational burden and memory requirements when implementing CNNs. To approach this goal, FPGA-QNN exploits the basics of quantized neural network (QNN) models by converting the high burden of full-precision weights and activations into integer operations. The FPGA-QNN framework comes up with 12 accelerators based on multi-layer perceptron (MLP) and LeNet CNN models, each of which is associated with a specific combination of quantization and folding. The outputs from the performance evaluations on Xilinx PYNQ Z1 development board proved the superiority of FPGA-QNN in terms of resource utilization and energy efficiency in comparison to several recent approaches. The proposed MLP model classified the FashionMNIST dataset at a speed of 953 kFPS with 1019 GOPs while consuming 2.05 W.https://www.mdpi.com/2076-3417/15/2/688acceleratorFPGAQNNdeep learningFINN |
| spellingShingle | Mustafa Tasci Ayhan Istanbullu Vedat Tumen Selahattin Kosunalp FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs Applied Sciences accelerator FPGA QNN deep learning FINN |
| title | FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs |
| title_full | FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs |
| title_fullStr | FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs |
| title_full_unstemmed | FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs |
| title_short | FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs |
| title_sort | fpga qnn quantized neural network hardware acceleration on fpgas |
| topic | accelerator FPGA QNN deep learning FINN |
| url | https://www.mdpi.com/2076-3417/15/2/688 |
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