Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching

Dynamically and partially reconfigurable Field Programmable Gate Arrays (FPGAs) offer high performances and flexibility. These platforms can hot-swap reconfigurable regions to change the hardware behavior at the cost of a reconfiguration process. The scheduling of applications and their reconfigurat...

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Main Authors: Alexis Duhamel, Sebastien Pillement
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/10769450/
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author Alexis Duhamel
Sebastien Pillement
author_facet Alexis Duhamel
Sebastien Pillement
author_sort Alexis Duhamel
collection DOAJ
description Dynamically and partially reconfigurable Field Programmable Gate Arrays (FPGAs) offer high performances and flexibility. These platforms can hot-swap reconfigurable regions to change the hardware behavior at the cost of a reconfiguration process. The scheduling of applications and their reconfiguration processes are then essential to respect timing constraints. In this paper, we introduce PF-PEFT, a scheduling heuristic for dynamically reconfigurable FPGA architectures. Results show that our approach reduces schedules duration by up to 13% compared to a comparable state-of-the-art approach.
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spelling doaj-art-b3d8a0b44b4049e899dfc3f875a047d32025-08-20T02:38:15ZengIEEEIEEE Access2169-35362024-01-011218430318431010.1109/ACCESS.2024.350737610769450Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream PrefetchingAlexis Duhamel0https://orcid.org/0000-0002-7280-3094Sebastien Pillement1https://orcid.org/0000-0002-9160-2896CNRS, IETR UMR 6164, Nantes Université, Nantes, FranceCNRS, IETR UMR 6164, Nantes Université, Nantes, FranceDynamically and partially reconfigurable Field Programmable Gate Arrays (FPGAs) offer high performances and flexibility. These platforms can hot-swap reconfigurable regions to change the hardware behavior at the cost of a reconfiguration process. The scheduling of applications and their reconfiguration processes are then essential to respect timing constraints. In this paper, we introduce PF-PEFT, a scheduling heuristic for dynamically reconfigurable FPGA architectures. Results show that our approach reduces schedules duration by up to 13% compared to a comparable state-of-the-art approach.https://ieeexplore.ieee.org/document/10769450/DPRFPGAjust-in-time bitstream prefetchreconfigurable computingruntime scheduling
spellingShingle Alexis Duhamel
Sebastien Pillement
Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching
IEEE Access
DPR
FPGA
just-in-time bitstream prefetch
reconfigurable computing
runtime scheduling
title Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching
title_full Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching
title_fullStr Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching
title_full_unstemmed Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching
title_short Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching
title_sort runtime task scheduling for fpga based embedded systems using just in time bitstream prefetching
topic DPR
FPGA
just-in-time bitstream prefetch
reconfigurable computing
runtime scheduling
url https://ieeexplore.ieee.org/document/10769450/
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