Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA
Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on a...
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| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2013-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2013/834793 |
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| author | Nilanka Rajapaksha Amila Edirisuriya Arjuna Madanayake Renato J. Cintra Dennis Onen Ihab Amer Vassil S. Dimitrov |
| author_facet | Nilanka Rajapaksha Amila Edirisuriya Arjuna Madanayake Renato J. Cintra Dennis Onen Ihab Amer Vassil S. Dimitrov |
| author_sort | Nilanka Rajapaksha |
| collection | DOAJ |
| description | Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltage-temperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transform coefficients having error within 1%. The performance of the 65 nm asynchronous hardware in terms of speed of operation is investigated and compared with the 65 nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracy
improvements obtained. |
| format | Article |
| id | doaj-art-b37de75ff01f4d77a333309358b1c7d6 |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-b37de75ff01f4d77a333309358b1c7d62025-02-03T05:49:27ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552013-01-01201310.1155/2013/834793834793Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGANilanka Rajapaksha0Amila Edirisuriya1Arjuna Madanayake2Renato J. Cintra3Dennis Onen4Ihab Amer5Vassil S. Dimitrov6Electrical and Computer Engineering, Auburn Science and Engineering Center (ASEC) 265, The University of Akron, Akron, OH 44325-3904, USAElectrical and Computer Engineering, Auburn Science and Engineering Center (ASEC) 265, The University of Akron, Akron, OH 44325-3904, USAElectrical and Computer Engineering, Auburn Science and Engineering Center (ASEC) 265, The University of Akron, Akron, OH 44325-3904, USASignal Processing Group, Department of Statistics, Federal University of Pernambuco, 50740-540 Recife, PE, BrazilDepartment of Electrical and Computer Engineering, ICT 402, Schulich School of Engineering, University of Calgary, 2500 University Drive NW Calgary, Alberta, Calgary, AB, T2N 1N4, CanadaAdvanced Micro Devices, 1 Commerce Valley Drive East, Markham, ON, L3T 7X6, CanadaDepartment of Electrical and Computer Engineering, ICT 402, Schulich School of Engineering, University of Calgary, 2500 University Drive NW Calgary, Alberta, Calgary, AB, T2N 1N4, CanadaTransformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltage-temperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transform coefficients having error within 1%. The performance of the 65 nm asynchronous hardware in terms of speed of operation is investigated and compared with the 65 nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracy improvements obtained.http://dx.doi.org/10.1155/2013/834793 |
| spellingShingle | Nilanka Rajapaksha Amila Edirisuriya Arjuna Madanayake Renato J. Cintra Dennis Onen Ihab Amer Vassil S. Dimitrov Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA Journal of Electrical and Computer Engineering |
| title | Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA |
| title_full | Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA |
| title_fullStr | Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA |
| title_full_unstemmed | Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA |
| title_short | Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA |
| title_sort | asynchronous realization of algebraic integer based 2d dct using achronix speedster spd60 fpga |
| url | http://dx.doi.org/10.1155/2013/834793 |
| work_keys_str_mv | AT nilankarajapaksha asynchronousrealizationofalgebraicintegerbased2ddctusingachronixspeedsterspd60fpga AT amilaedirisuriya asynchronousrealizationofalgebraicintegerbased2ddctusingachronixspeedsterspd60fpga AT arjunamadanayake asynchronousrealizationofalgebraicintegerbased2ddctusingachronixspeedsterspd60fpga AT renatojcintra asynchronousrealizationofalgebraicintegerbased2ddctusingachronixspeedsterspd60fpga AT dennisonen asynchronousrealizationofalgebraicintegerbased2ddctusingachronixspeedsterspd60fpga AT ihabamer asynchronousrealizationofalgebraicintegerbased2ddctusingachronixspeedsterspd60fpga AT vassilsdimitrov asynchronousrealizationofalgebraicintegerbased2ddctusingachronixspeedsterspd60fpga |