One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection
Memory technologies for in-memory computing (IMC) based neural network (NN) operations in edge devices face two primary challenges. First, these technologies often exhibit an excessive average power due to the high currents in the memory’s low and high resistance state (LRS and HRS). Seco...
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IEEE
2025-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10771781/ |
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| author | Shreyas Deshmukh Ankit Bende Diti Sanghai Vivek Saraswat Anmol Biswas Abhishek Kadam Shubham Patil Ajay Kumar Singh Veeresh Deshpande Udayan Ganguly |
| author_facet | Shreyas Deshmukh Ankit Bende Diti Sanghai Vivek Saraswat Anmol Biswas Abhishek Kadam Shubham Patil Ajay Kumar Singh Veeresh Deshpande Udayan Ganguly |
| author_sort | Shreyas Deshmukh |
| collection | DOAJ |
| description | Memory technologies for in-memory computing (IMC) based neural network (NN) operations in edge devices face two primary challenges. First, these technologies often exhibit an excessive average power due to the high currents in the memory’s low and high resistance state (LRS and HRS). Second, their vulnerability to tampering compromises device reliability in security-sensitive Internet of Things (IoT) applications. To tackle these challenges, we propose the use of one-time programmable memory (OTPM) for IMC-based thermal attack-secured and ultra-low powered NN accelerator with write disablement to prevent re-programming/tampering. In this article, first, we show that HRS for OTP memory is exceptionally high (~190 M<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula>), but the higher current in LRS (~100 mA) presents a challenge of high average power. We address this challenge by introducing a select transistor gate voltage biasing scheme with the 1T-1OTPM bit cell to reduce LRS current significantly while still trading off the excessive HRS/LRS ratio of 1.5 M to about 1 k. This reduces average power by <inline-formula> <tex-math notation="LaTeX">$\sim 1000\times $ </tex-math></inline-formula> without degrading CIFAR-10 classification performance. Second, we evaluate the impact of OTPM size scaling on HRS and LRS distributions. Though scaling reduces HRS current, we show that moderately scaled 10F<inline-formula> <tex-math notation="LaTeX">$\times 10$ </tex-math></inline-formula>F OTPM bit cells produce the lowest maximum current in HRS compared to the more aggressively scaled 1F<inline-formula> <tex-math notation="LaTeX">$\times 1$ </tex-math></inline-formula>F, which suffers from significant process-induced variability. Third, we show the robustness to temperature, which enables security from thermal attacks. |
| format | Article |
| id | doaj-art-b1179f8afcd149c7a234e2bd1ff32a07 |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-b1179f8afcd149c7a234e2bd1ff32a072025-08-20T03:34:25ZengIEEEIEEE Journal of the Electron Devices Society2168-67342025-01-011385486210.1109/JEDS.2024.350875910771781One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault InjectionShreyas Deshmukh0https://orcid.org/0000-0003-0086-1276Ankit Bende1Diti Sanghai2Vivek Saraswat3https://orcid.org/0000-0001-9191-1632Anmol Biswas4https://orcid.org/0000-0002-2363-5864Abhishek Kadam5https://orcid.org/0000-0001-6106-5623Shubham Patil6https://orcid.org/0000-0003-2375-481XAjay Kumar Singh7https://orcid.org/0000-0002-6170-1340Veeresh Deshpande8Udayan Ganguly9https://orcid.org/0000-0002-1498-5993Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaMemory technologies for in-memory computing (IMC) based neural network (NN) operations in edge devices face two primary challenges. First, these technologies often exhibit an excessive average power due to the high currents in the memory’s low and high resistance state (LRS and HRS). Second, their vulnerability to tampering compromises device reliability in security-sensitive Internet of Things (IoT) applications. To tackle these challenges, we propose the use of one-time programmable memory (OTPM) for IMC-based thermal attack-secured and ultra-low powered NN accelerator with write disablement to prevent re-programming/tampering. In this article, first, we show that HRS for OTP memory is exceptionally high (~190 M<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula>), but the higher current in LRS (~100 mA) presents a challenge of high average power. We address this challenge by introducing a select transistor gate voltage biasing scheme with the 1T-1OTPM bit cell to reduce LRS current significantly while still trading off the excessive HRS/LRS ratio of 1.5 M to about 1 k. This reduces average power by <inline-formula> <tex-math notation="LaTeX">$\sim 1000\times $ </tex-math></inline-formula> without degrading CIFAR-10 classification performance. Second, we evaluate the impact of OTPM size scaling on HRS and LRS distributions. Though scaling reduces HRS current, we show that moderately scaled 10F<inline-formula> <tex-math notation="LaTeX">$\times 10$ </tex-math></inline-formula>F OTPM bit cells produce the lowest maximum current in HRS compared to the more aggressively scaled 1F<inline-formula> <tex-math notation="LaTeX">$\times 1$ </tex-math></inline-formula>F, which suffers from significant process-induced variability. Third, we show the robustness to temperature, which enables security from thermal attacks.https://ieeexplore.ieee.org/document/10771781/Artificial neural networkin-memory computationnon-volatile memoryone time programmable memorysecured memory technology |
| spellingShingle | Shreyas Deshmukh Ankit Bende Diti Sanghai Vivek Saraswat Anmol Biswas Abhishek Kadam Shubham Patil Ajay Kumar Singh Veeresh Deshpande Udayan Ganguly One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection IEEE Journal of the Electron Devices Society Artificial neural network in-memory computation non-volatile memory one time programmable memory secured memory technology |
| title | One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection |
| title_full | One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection |
| title_fullStr | One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection |
| title_full_unstemmed | One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection |
| title_short | One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection |
| title_sort | one time programmable memory for ultra low power ann inference accelerator with security against thermal fault injection |
| topic | Artificial neural network in-memory computation non-volatile memory one time programmable memory secured memory technology |
| url | https://ieeexplore.ieee.org/document/10771781/ |
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