Structure and Principles of Operation of a Quaternion VLSI Multiplier
The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed al...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2024-09-01
|
| Series: | Applied Sciences |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2076-3417/14/18/8123 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1850259016758853632 |
|---|---|
| author | Aleksandr Cariow Mariusz Naumowicz Andrzej Handkiewicz |
| author_facet | Aleksandr Cariow Mariusz Naumowicz Andrzej Handkiewicz |
| author_sort | Aleksandr Cariow |
| collection | DOAJ |
| description | The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>130</mn><mspace width="3.33333pt"></mspace><mi>nm</mi></mrow></semantics></math></inline-formula> technology. The developed scripts in VHDL are available in the GitHub repository. |
| format | Article |
| id | doaj-art-b0f84f5b387b41ae8e4bc7d5a8bf8de6 |
| institution | OA Journals |
| issn | 2076-3417 |
| language | English |
| publishDate | 2024-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj-art-b0f84f5b387b41ae8e4bc7d5a8bf8de62025-08-20T01:55:58ZengMDPI AGApplied Sciences2076-34172024-09-011418812310.3390/app14188123Structure and Principles of Operation of a Quaternion VLSI MultiplierAleksandr Cariow0Mariusz Naumowicz1Andrzej Handkiewicz2Faculty of Computer Science and Information Technology, West Pomeranian University of Technology, 70-310 Szczecin, PolandFaculty of Computing, Poznań University of Technology, ul. Piotrowo 3a, 60-965 Poznań, PolandFaculty of Technology, The Jacob of Paradise University, 66-400 Gorzów Wielkopolski, PolandThe paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>130</mn><mspace width="3.33333pt"></mspace><mi>nm</mi></mrow></semantics></math></inline-formula> technology. The developed scripts in VHDL are available in the GitHub repository.https://www.mdpi.com/2076-3417/14/18/8123hypercomplex numbersquaternion multiplierfast algorithmmatrix–vector multiplicationhardware implementationFPGA |
| spellingShingle | Aleksandr Cariow Mariusz Naumowicz Andrzej Handkiewicz Structure and Principles of Operation of a Quaternion VLSI Multiplier Applied Sciences hypercomplex numbers quaternion multiplier fast algorithm matrix–vector multiplication hardware implementation FPGA |
| title | Structure and Principles of Operation of a Quaternion VLSI Multiplier |
| title_full | Structure and Principles of Operation of a Quaternion VLSI Multiplier |
| title_fullStr | Structure and Principles of Operation of a Quaternion VLSI Multiplier |
| title_full_unstemmed | Structure and Principles of Operation of a Quaternion VLSI Multiplier |
| title_short | Structure and Principles of Operation of a Quaternion VLSI Multiplier |
| title_sort | structure and principles of operation of a quaternion vlsi multiplier |
| topic | hypercomplex numbers quaternion multiplier fast algorithm matrix–vector multiplication hardware implementation FPGA |
| url | https://www.mdpi.com/2076-3417/14/18/8123 |
| work_keys_str_mv | AT aleksandrcariow structureandprinciplesofoperationofaquaternionvlsimultiplier AT mariusznaumowicz structureandprinciplesofoperationofaquaternionvlsimultiplier AT andrzejhandkiewicz structureandprinciplesofoperationofaquaternionvlsimultiplier |