Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration
This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system called RAMPSoC. The processing elements, also c...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2012-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2012/298561 |
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| _version_ | 1832558821150556160 |
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| author | Diana Göhringer Lukas Meder Stephan Werner Oliver Oey Jürgen Becker Michael Hübner |
| author_facet | Diana Göhringer Lukas Meder Stephan Werner Oliver Oey Jürgen Becker Michael Hübner |
| author_sort | Diana Göhringer |
| collection | DOAJ |
| description | This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system called RAMPSoC. The processing elements, also called clients, can access the memory core via the Network-on-Chip (NoC). The memory core supports a dynamic mapping of an address space for the different clients as well as different data transfer modes, such as variable burst sizes. Therefore, two main limitations of FPGA-based multiprocessor systems, the restricted on-chip memory resources and that usually only one physical channel to an off-chip memory exists, are leveraged. Furthermore, a software abstraction layer is introduced, which hides the complexity of the memory core architecture and which provides an easy to use interface for the application programmer. Finally, the advantages of the novel memory core in terms of performance, flexibility, and user friendliness are shown using a real-world image processing application. |
| format | Article |
| id | doaj-art-b045ed815cb84968873f9f92fb860484 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-b045ed815cb84968873f9f92fb8604842025-02-03T01:31:36ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092012-01-01201210.1155/2012/298561298561Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application ExplorationDiana Göhringer0Lukas Meder1Stephan Werner2Oliver Oey3Jürgen Becker4Michael Hübner5Institute for Data Processing and Electronics, Karlsruhe Institute of Technology, 76344 Eggenstein-Leopoldshafen, GermanyInstitute for Information Processing Technology, Karlsruhe Institute of Technology, 76128 Karlsruhe, GermanyInstitute for Information Processing Technology, Karlsruhe Institute of Technology, 76128 Karlsruhe, GermanyInstitute for Information Processing Technology, Karlsruhe Institute of Technology, 76128 Karlsruhe, GermanyInstitute for Information Processing Technology, Karlsruhe Institute of Technology, 76128 Karlsruhe, GermanyChair for Embedded Systems in Information Technology, Ruhr-University of Bochum, 44780 Bochum, GermanyThis paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system called RAMPSoC. The processing elements, also called clients, can access the memory core via the Network-on-Chip (NoC). The memory core supports a dynamic mapping of an address space for the different clients as well as different data transfer modes, such as variable burst sizes. Therefore, two main limitations of FPGA-based multiprocessor systems, the restricted on-chip memory resources and that usually only one physical channel to an off-chip memory exists, are leveraged. Furthermore, a software abstraction layer is introduced, which hides the complexity of the memory core architecture and which provides an easy to use interface for the application programmer. Finally, the advantages of the novel memory core in terms of performance, flexibility, and user friendliness are shown using a real-world image processing application.http://dx.doi.org/10.1155/2012/298561 |
| spellingShingle | Diana Göhringer Lukas Meder Stephan Werner Oliver Oey Jürgen Becker Michael Hübner Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration International Journal of Reconfigurable Computing |
| title | Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration |
| title_full | Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration |
| title_fullStr | Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration |
| title_full_unstemmed | Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration |
| title_short | Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration |
| title_sort | adaptive multiclient network on chip memory core hardware architecture software abstraction layer and application exploration |
| url | http://dx.doi.org/10.1155/2012/298561 |
| work_keys_str_mv | AT dianagohringer adaptivemulticlientnetworkonchipmemorycorehardwarearchitecturesoftwareabstractionlayerandapplicationexploration AT lukasmeder adaptivemulticlientnetworkonchipmemorycorehardwarearchitecturesoftwareabstractionlayerandapplicationexploration AT stephanwerner adaptivemulticlientnetworkonchipmemorycorehardwarearchitecturesoftwareabstractionlayerandapplicationexploration AT oliveroey adaptivemulticlientnetworkonchipmemorycorehardwarearchitecturesoftwareabstractionlayerandapplicationexploration AT jurgenbecker adaptivemulticlientnetworkonchipmemorycorehardwarearchitecturesoftwareabstractionlayerandapplicationexploration AT michaelhubner adaptivemulticlientnetworkonchipmemorycorehardwarearchitecturesoftwareabstractionlayerandapplicationexploration |