Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation
Abstract Information security is essential to ensure security of exchanged sensitive data in resource‐constrained devices (RCDs) because they are used widely in the Internet of things (IoT). The implementation of special ciphers is required in these RCDs, as they have many limitations and constraint...
Saved in:
Main Authors: | Sa'ed Abed, Reem Jaffal, Bassam Jamil Mohd, Mohammad Alshayeji |
---|---|
Format: | Article |
Language: | English |
Published: |
Wiley
2021-03-01
|
Series: | IET Circuits, Devices and Systems |
Subjects: | |
Online Access: | https://doi.org/10.1049/cds2.12011 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture
by: Xiaoying Huang, et al.
Published: (2021-11-01) -
Field‐programmable gate array acceleration of the Tersoff potential in LAMMPS
by: Quan Deng, et al.
Published: (2025-01-01) -
Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme
by: Saeideh Sheikhpur, et al.
Published: (2021-11-01) -
Fast approximation of the top‐k items in data streams using FPGAs
by: Ali Ebrahim, et al.
Published: (2023-03-01) -
Field-Programmable Gate Array (FPGA)-Based Lock-In Amplifier System with Signal Enhancement: A Comprehensive Review on the Design for Advanced Measurement Applications
by: Jose Alejandro Galaviz-Aguilar, et al.
Published: (2025-01-01)