VLSI implementation of AES algorithm against differential power attack and differential fault attack
A VLSI implementation of AES algorithm against both differential power attack and differential fault attack was proposed. The main countermeasures employed in this hardware design are masking technique and two-dimensional parity-based concurrent error detection method. And exploits such methods as s...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | zho |
| Published: |
Editorial Department of Journal on Communications
2010-01-01
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| Series: | Tongxin xuebao |
| Subjects: | |
| Online Access: | http://www.joconline.com.cn/zh/article/74650743/ |
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