A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage
Abstract The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research report...
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| Language: | English |
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Wiley
2021-01-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/cds2.12008 |
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| author | Jérôme K. Folla Maria L. Crespo Evariste T. Wembe Mohammad A. S. Bhuiyan Andres Cicuttin Bernard Z. Essimbi Mamun B. I. Reaz |
| author_facet | Jérôme K. Folla Maria L. Crespo Evariste T. Wembe Mohammad A. S. Bhuiyan Andres Cicuttin Bernard Z. Essimbi Mamun B. I. Reaz |
| author_sort | Jérôme K. Folla |
| collection | DOAJ |
| description | Abstract The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research reports the design and implementation of a low‐offset, low‐power and high‐speed dynamic latch comparator. In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to improve the power dissipation and the comparison speed of the device. A custom latch structure with rigorous transistor sizing was implemented to avoid short circuit current and mismatch in the module. The effective trans‐conductance of the cross‐coupled transistors of the latch was therefore improved for an optimal time delay solution. The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post‐layout simulation results in 65 nm CMOS technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low‐offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. Moreover, the core circuit layout occupies only 183.3 μm2. |
| format | Article |
| id | doaj-art-a943c9e5961042da96b09e89c39d3a92 |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2021-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-a943c9e5961042da96b09e89c39d3a922025-02-03T01:29:38ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982021-01-01151657710.1049/cds2.12008A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stageJérôme K. Folla0Maria L. Crespo1Evariste T. Wembe2Mohammad A. S. Bhuiyan3Andres Cicuttin4Bernard Z. Essimbi5Mamun B. I. Reaz6Department of Physics Laboratory of Energy Electrical and Electronics Systems University of Yaoundé I Yaoundé CameroonMultidisciplinary Laboratory (MLAB), International Centre for Theoretical Physics (ICTP) Trieste ItalyDepartment of Physics Laboratory of Electronics and Automatics University of Douala Douala CameroonElectrical and Electronics Engineering Xiamen University Malaysia Sepang Selangor MalaysiaMultidisciplinary Laboratory (MLAB), International Centre for Theoretical Physics (ICTP) Trieste ItalyDepartment of Physics Laboratory of Energy Electrical and Electronics Systems University of Yaoundé I Yaoundé CameroonElectrical, Electronic and Systems Engineering Universiti Kebangsaan Malaysia Bangi Selangor MalaysiaAbstract The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research reports the design and implementation of a low‐offset, low‐power and high‐speed dynamic latch comparator. In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to improve the power dissipation and the comparison speed of the device. A custom latch structure with rigorous transistor sizing was implemented to avoid short circuit current and mismatch in the module. The effective trans‐conductance of the cross‐coupled transistors of the latch was therefore improved for an optimal time delay solution. The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post‐layout simulation results in 65 nm CMOS technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low‐offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. Moreover, the core circuit layout occupies only 183.3 μm2.https://doi.org/10.1049/cds2.12008clocksCMOS logic circuitscomparators (circuits)flip‐flopshigh‐speed integrated circuitsintegrated circuit layout |
| spellingShingle | Jérôme K. Folla Maria L. Crespo Evariste T. Wembe Mohammad A. S. Bhuiyan Andres Cicuttin Bernard Z. Essimbi Mamun B. I. Reaz A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage IET Circuits, Devices and Systems clocks CMOS logic circuits comparators (circuits) flip‐flops high‐speed integrated circuits integrated circuit layout |
| title | A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage |
| title_full | A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage |
| title_fullStr | A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage |
| title_full_unstemmed | A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage |
| title_short | A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage |
| title_sort | low offset low power and high speed dynamic latch comparator with a preamplifier enhanced stage |
| topic | clocks CMOS logic circuits comparators (circuits) flip‐flops high‐speed integrated circuits integrated circuit layout |
| url | https://doi.org/10.1049/cds2.12008 |
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