Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs
We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed-point implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath formed of wordlength-wise resources (i.e., functional units...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2009-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2009/703267 |
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| Summary: | We address the
automatic synthesis of DSP algorithms using
FPGAs. Optimized fixed-point
implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath
formed of wordlength-wise resources (i.e., functional units, multiplexers, and registers); (iii) an FPGA-wise resource
usage metric that enables an efficient distribution of logic fabric and embedded DSP resources.
The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-point
datapaths and (ii) the benefits of a wise use of embedded FPGA resources. The use of a complete fixed-point datapath
leads to improvements up to 35%. And, the wise mapping of operations to FPGA resources (logic fabric and embedded
blocks), thanks to the proposed resource usage metric, leads to improvements up to 54%. |
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| ISSN: | 1687-7195 1687-7209 |