Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence
This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to di...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2013-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2013/905057 |
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| _version_ | 1849399212706365440 |
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| author | Xabier Iturbe Khaled Benkrid Chuan Hong Ali Ebrahim Tughrul Arslan Imanol Martinez |
| author_facet | Xabier Iturbe Khaled Benkrid Chuan Hong Ali Ebrahim Tughrul Arslan Imanol Martinez |
| author_sort | Xabier Iturbe |
| collection | DOAJ |
| description | This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail in this article. These algorithms consider most of the technological constraints existing in modern partially reconfigurable FPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition, the algorithms target other important aspects such as communications and synchronization among the different computations that are carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide range of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined. |
| format | Article |
| id | doaj-art-9d6538b78142467483d9e1d6f152e005 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-9d6538b78142467483d9e1d6f152e0052025-08-20T03:38:23ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092013-01-01201310.1155/2013/905057905057Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault OccurrenceXabier Iturbe0Khaled Benkrid1Chuan Hong2Ali Ebrahim3Tughrul Arslan4Imanol Martinez5Embedded System-on-Chip Group, IKERLAN-IK4 Research Alliance, 20500 Mondragón, SpainSystem Level Integration Group, The University of Edinburgh, Edinburgh EH9 3JL, UKSystem Level Integration Group, The University of Edinburgh, Edinburgh EH9 3JL, UKSystem Level Integration Group, The University of Edinburgh, Edinburgh EH9 3JL, UKSystem Level Integration Group, The University of Edinburgh, Edinburgh EH9 3JL, UKEmbedded System-on-Chip Group, IKERLAN-IK4 Research Alliance, 20500 Mondragón, SpainThis paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail in this article. These algorithms consider most of the technological constraints existing in modern partially reconfigurable FPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition, the algorithms target other important aspects such as communications and synchronization among the different computations that are carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide range of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined.http://dx.doi.org/10.1155/2013/905057 |
| spellingShingle | Xabier Iturbe Khaled Benkrid Chuan Hong Ali Ebrahim Tughrul Arslan Imanol Martinez Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence International Journal of Reconfigurable Computing |
| title | Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence |
| title_full | Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence |
| title_fullStr | Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence |
| title_full_unstemmed | Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence |
| title_short | Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence |
| title_sort | runtime scheduling allocation and execution of real time hardware tasks onto xilinx fpgas subject to fault occurrence |
| url | http://dx.doi.org/10.1155/2013/905057 |
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